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公开(公告)号:US10714425B2
公开(公告)日:2020-07-14
申请号:US15263632
申请日:2016-09-13
Applicant: Apple Inc.
Inventor: Sanjay Dabral
IPC: H01L23/367 , H01L23/34 , H01L25/065 , H01L23/538 , H01L23/427 , H01L23/28 , H01L23/13 , H01L23/00
Abstract: In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.
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公开(公告)号:US20200075497A1
公开(公告)日:2020-03-05
申请号:US16583082
申请日:2019-09-25
Applicant: Apple Inc.
Inventor: Sanjay Dabral , Jun Zhai
IPC: H01L23/538 , H01L23/488 , H01L23/00 , H01L25/18 , H01L21/66 , H01L23/522 , H01L23/528 , H01L23/58
Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
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公开(公告)号:US10566286B2
公开(公告)日:2020-02-18
申请号:US16250854
申请日:2019-01-17
Applicant: Apple Inc.
Inventor: Sanjay Dabral , David A. Secker , Huabo Chen , Zhenggang Cheng
IPC: H01L23/52 , H01L23/538 , H01L23/498 , H01L23/14 , H01L23/00 , H01L25/065
Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.
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公开(公告)号:US10438896B2
公开(公告)日:2019-10-08
申请号:US15801163
申请日:2017-11-01
Applicant: Apple Inc.
Inventor: Sanjay Dabral , Zun Zhai
IPC: H01L23/48 , H01L21/44 , H01L23/538 , H01L23/488 , H01L23/00 , H01L25/18 , H01L23/522 , H01L23/58 , H01L21/66 , H01L23/528
Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
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公开(公告)号:US09509490B1
公开(公告)日:2016-11-29
申请号:US14859757
申请日:2015-09-21
Applicant: Apple Inc.
Inventor: Sanjay Dabral
CPC classification number: H04L7/0008 , G06F1/04 , H03L7/16 , H04L7/0091
Abstract: A system for sharing a reference clock signal between multiple devices is disclosed. The system includes a source device, and a plurality of destination devices. The source device may be configured to generate a reference clock signal and transmit data via a communication link. The reference clock signal may include first and second phases, and the second phase may be an inverse of the first phase. A filter unit configured to filter the reference clock signal may be coupled between the first and second phases of the reference clock signal. Each destination device may be configured to receive the reference clock signal and receive the data dependent upon the reference clock signal.
Abstract translation: 公开了一种用于在多个设备之间共享参考时钟信号的系统。 该系统包括源设备和多个目的设备。 源设备可以被配置为生成参考时钟信号并且经由通信链路发送数据。 参考时钟信号可以包括第一和第二相位,第二相位可以是第一相位的倒数。 被配置为对参考时钟信号进行滤波的滤波器单元可以耦合在参考时钟信号的第一和第二相位之间。 每个目的地设备可以被配置为接收参考时钟信号并且接收依赖于参考时钟信号的数据。
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