公开(公告)号：US12237269B2

公开(公告)日：2025-02-25

申请号：US17655157

申请日：2022-03-16

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Ravindranath T. Kollipara

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

公开(公告)号：US12087689B2

公开(公告)日：2024-09-10

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US20240088779A1

公开(公告)日：2024-03-14

申请号：US18471868

申请日：2023-09-21

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Sanjay Dabral

IPC: H02M1/15 ,  G06F1/3206 ,  H02M3/158

CPC classification number: H02M1/15 ,  G06F1/3206 ,  H02M3/1582

Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

公开(公告)号：US20230402373A1

公开(公告)日：2023-12-14

申请号：US18339132

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/585 ,  H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/08 ,  H01L2224/32145 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/08145

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20230299007A1

公开(公告)日：2023-09-21

申请号：US17655157

申请日：2022-03-16

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Ravindranath T. Kollipara

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L23/5389 ,  H01L2924/1432 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/30105 ,  H01L2924/30205 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1601 ,  H01L2224/1703

Abstract: Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

公开(公告)号：US20230085890A1

公开(公告)日：2023-03-23

申请号：US17483535

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/58 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11476203B2

公开(公告)日：2022-10-18

申请号：US17216278

申请日：2021-03-29

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US10756622B2

公开(公告)日：2020-08-25

申请号：US16231904

申请日：2018-12-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US10742217B2

公开(公告)日：2020-08-11

申请号：US16266604

申请日：2019-02-04

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20170154664A1

公开(公告)日：2017-06-01

申请号：US15430747

申请日：2017-02-13

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: G11C11/4074 ,  G11C14/00

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C7/02 ,  G11C14/0018 ,  G11C29/021 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.