公开(公告)号：US4620211A

公开(公告)日：1986-10-28

申请号：US640280

申请日：1984-08-13

申请人： Bantval J. Baliga ,  Victor A. K. Temple ,  Tat-Sing P. Chow

发明人： Bantval J. Baliga ,  Victor A. K. Temple ,  Tat-Sing P. Chow

IPC分类号： H01L21/263 ,  H01L29/167 ,  H01L29/32 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74

CPC分类号： H01L29/7802 ,  H01L21/263 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7395

摘要： Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region constituting current carrier recombination centers, form a layer with a peak concentration situated in proximity to the emitter-base junction of the inherent bipolar transistor. The layer of ions is of small thickness, whereby the resulting increase in the respective sheet resistances of the emitter and base layers to either side of the emitter-base junction is minimized.

摘要翻译： 通过将选择的离子注入到这种器件的半导体材料中，实现诸如IGT或IGFET之类的绝缘栅极半导体器件中的固有双极晶体管的正向电流增益的降低。 在构成电流载流子复合中心的注入区域中产生缺陷的离子形成具有位于本征双极晶体管的发射极 - 基极结附近的峰值浓度的层。 离子层的厚度很小，从而使发射极和基极层相对于发射极 - 基极结的任一侧的各个薄层电阻的增加最小化。

公开(公告)号：US4587712A

公开(公告)日：1986-05-13

申请号：US692073

申请日：1985-01-17

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L21/332 ,  H01L21/335 ,  H01L21/74 ,  H01L29/10 ,  H01L21/20

CPC分类号： H01L29/66363 ,  H01L21/743 ,  H01L29/1066 ,  H01L29/66416

摘要： A vertical channel junction gate electric field controlled device (e.g., a field effect transistor, or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves, generally on the upper surface of the base region layer, are upper electrode regions, for example, source electrode regions or cathode electrode regions. Recessed in the grooves are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions in the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the location of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization.

摘要翻译： 垂直沟道结栅电场控制装置（例如，场效应晶体管或场控晶闸管）包括半导体基极区域层和形成在基极区域层的上表面中的具有垂直壁的多个沟槽。 通常在基底区域的上表面上的凹槽之间是上电极区域，例如源电极区域或阴极电极区域。 嵌入凹槽中的是结栅区域。 上电极端子金属化通常在上部器件层上蒸发，并且栅极端子金属化在沟槽中的结栅区域之上。 因此，所公开的结构沿着用于低电阻栅极连接的凹入栅极区域具有连续的金属化。 该结构有利于通过还公开的方法进行制造，其避免了掩模中的任何关键的光刻对准步骤以限定源极（或阴极）和栅极区域的位置，并且避免了在形成电极时需要用于金属界定的任何掩模或掩模对准 金属化。

公开(公告)号：US4567641A

公开(公告)日：1986-02-04

申请号：US650314

申请日：1984-09-12

申请人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

发明人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L21/441 ,  H01L21/465

CPC分类号： H01L21/30608 ,  H01L21/308 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/41766 ,  H01L29/4975

摘要： An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

摘要翻译： 公开了一种具有减小长度的扩散区域的改进的半导体器件和制造这种半导体器件的改进方法。 作为示例，半导体器件可以是MOSFET或IGR。 以制造MOSFET的方法的形式，N + SOURCE通过扩散掩模的窗口扩散到P BASE中。 各向异性或定向蚀刻剂通过相同的窗口施加到N + SOURCE。 蚀刻剂除去大部分N + SOURCE，但允许其肩部保持完整。 构成完成的N + SOURCE区域的这些肩部的长度减小，大大降低了MOSFET中寄生双极晶体管导通的风险。 当通过改进的方法制造IGR时，IGR中的寄生双极晶体管的导通的风险也同样降低。

公开(公告)号：US4506282A

公开(公告)日：1985-03-19

申请号：US455174

申请日：1983-01-03

申请人： Bantval J. Baliga

发明人： Bantval J. Baliga

IPC分类号： H01L29/80 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/07 ,  H01L29/73 ,  H03K17/567 ,  H01L29/72

CPC分类号： H03K17/567 ,  H01L27/0722

摘要： A semiconductor device incorporates a JFET serially connected to a bipolar transistor to achieve normally-off operation. An impedance element is connected between the base of the bipolar transistor and the gate of the JFET, which serves as a single control electrode for the entire device. When a current is supplied to the control electrode, the bipolar transistor and JFET are both switched to the on state. In the JFET, the p-N junction between the gate region and the channel region is sufficiently forward-biased so as to inject current carriers into its channel region and markedly reduce the device on-resistance. An electrical circuit analogue of the device achieves the advantage of low on-resistance and normally-off operation.

摘要翻译： 半导体器件包括串联连接到双极晶体管的JFET以实现常关断操作。 阻抗元件连接在双极晶体管的基极和JFET的栅极之间，JFET用作整个器件的单个控制电极。 当电流被提供给控制电极时，双极晶体管和JFET都被切换到导通状态。 在JFET中，栅极区域和沟道区域之间的p-N结被充分正向偏置，以便将电流载流子注入其沟道区域并显着地减小器件导通电阻。 器件的电路模拟实现了低导通电阻和常闭操作的优点。