公开(公告)号：US4620211A

公开(公告)日：1986-10-28

申请号：US640280

申请日：1984-08-13

申请人： Bantval J. Baliga ,  Victor A. K. Temple ,  Tat-Sing P. Chow

发明人： Bantval J. Baliga ,  Victor A. K. Temple ,  Tat-Sing P. Chow

IPC分类号： H01L21/263 ,  H01L29/167 ,  H01L29/32 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74

CPC分类号： H01L29/7802 ,  H01L21/263 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7395

摘要： Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region constituting current carrier recombination centers, form a layer with a peak concentration situated in proximity to the emitter-base junction of the inherent bipolar transistor. The layer of ions is of small thickness, whereby the resulting increase in the respective sheet resistances of the emitter and base layers to either side of the emitter-base junction is minimized.

摘要翻译： 通过将选择的离子注入到这种器件的半导体材料中，实现诸如IGT或IGFET之类的绝缘栅极半导体器件中的固有双极晶体管的正向电流增益的降低。 在构成电流载流子复合中心的注入区域中产生缺陷的离子形成具有位于本征双极晶体管的发射极 - 基极结附近的峰值浓度的层。 离子层的厚度很小，从而使发射极和基极层相对于发射极 - 基极结的任一侧的各个薄层电阻的增加最小化。

公开(公告)号：US4823176A

公开(公告)日：1989-04-18

申请号：US33952

申请日：1987-04-03

申请人： Bantval J. Baliga ,  Tat-Sing P. Chow ,  Hsueh-Rong Chang

发明人： Bantval J. Baliga ,  Tat-Sing P. Chow ,  Hsueh-Rong Chang

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/44

CPC分类号： H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/4238

摘要： A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of the device. The figure preferably is everywhere convex and has a maximum width of substantially less than the depletion width, at breakdown, of a corresponding parallel plane junction. The device breakdown voltage is higher than the breakdown voltage of a corresponding junction having a cylindrical edge with a straight axis. In a preferred embodiment, the high voltage blocking junction has a plurality of such intersections with the device surface, each situated beneath a segment of the gate electrode. In a bipolar embodiment, the gate electrode may be omitted.

摘要翻译： 功率场效应器件具有与栅电极下方的器件表面相交的高电压阻挡连接。 该交点是一个闭平面几何图形，其中心在器件的体区内，而不是器件的更高掺杂的基极区域内。 该图优选地是凸起的，并且具有基本上小于相应的平行平面结的击穿时的耗尽宽度的最大宽度。 器件击穿电压高于具有直轴的圆柱形边缘的对应连接点的击穿电压。 在优选实施例中，高电压阻塞连接点具有与器件表面的多个这样的交点，每个交点位于栅电极的一段的下方。 在双极实施例中，可以省略栅电极。

公开(公告)号：US4998151A

公开(公告)日：1991-03-05

申请号：US337684

申请日：1989-04-13

申请人： Charles S. Korman ,  Krishna Shenai ,  Bantval J. Baliga ,  Patricia A. Piacente ,  Bernard Gorowitz ,  Tat-Sing P. Chow ,  Manjin J. Kim

发明人： Charles S. Korman ,  Krishna Shenai ,  Bantval J. Baliga ,  Patricia A. Piacente ,  Bernard Gorowitz ,  Tat-Sing P. Chow ,  Manjin J. Kim

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L29/45 ,  H01L29/745 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7455

摘要： A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this high conductivity layer allows a substantially smaller contact window to be employed for making contact between the final metallization and the source region. As a consequence, the aperture in the gate electrode and the cell size of the device can both be substantially reduced. The device has substantially improved operating characteristics. A method of producing the device is also described.

公开(公告)号：US4801986A

公开(公告)日：1989-01-31

申请号：US33940

申请日：1987-04-03

申请人： Hsueh-Rong Chang ,  Bantval J. Baliga ,  Tat-Sing P. Chow

发明人： Hsueh-Rong Chang ,  Bantval J. Baliga ,  Tat-Sing P. Chow

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7395

摘要： A power field effect device has a gate grid having a plurality of elongate openings therein through which a base region forming a high voltage blocking junction with the underlying body was diffused. The openings have round ends in order to prevent the formation of spherical portions in the high voltage blocking junction. The round ends of adjacent openings are positioned close enough to each other that their diffusion regions merge, thereby raising the device breakdown voltage to that of the cylindrical junction portion along the straight edges of the junction. In an alternative embodiment, the openings do not have round ends and are positioned close enough together that their diffusions merge end to end.

摘要翻译： 功率场效应器件具有栅极格栅，其中具有多个细长的开口，通过该栅极栅极与下面的主体形成高压阻挡连接处的基极区域被扩散。 这些开口具有圆形端部，以防止在高压阻塞连接处形成球形部分。 相邻开口的圆端彼此靠近，使其扩散区域合并，从而沿着连接点的直边缘将器件击穿电压提高到圆柱形接合部分的击穿电压。 在替代实施例中，开口不具有圆形端部并且被定位成足够接近，使得它们的扩散部分从一端到另一端合并。

公开(公告)号：US4717679A

公开(公告)日：1988-01-05

申请号：US935470

申请日：1986-11-26

申请人： Bantval J. Baliga ,  Tat-Sing P. Chow

发明人： Bantval J. Baliga ,  Tat-Sing P. Chow

IPC分类号： H01L21/033 ,  H01L21/331 ,  H01L29/739 ,  H01L21/38 ,  H01L21/425

CPC分类号： H01L29/66325 ,  H01L21/033 ,  H01L29/7393

摘要： An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.

摘要翻译： 公开了一种用于形成横向绝缘栅半导体器件的八掩模工艺。 栅极结构可以用作掩模以对准器件的第三和第五区域，并且第三保护层对准器件的第四和第六区域。

公开(公告)号：US4901127A

公开(公告)日：1990-02-13

申请号：US254897

申请日：1988-10-07

申请人： Tat-Sing P. Chow ,  Bantval J. Baliga

发明人： Tat-Sing P. Chow ,  Bantval J. Baliga

IPC分类号： H01L27/088 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L27/088 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/7802 ,  H01L29/7803

摘要： An IGBT and FET are integrated in a common semiconductor body and share common source/emitter, base and drift regions and an insulated gate electrode. The ON-resistance and turn-off time of this device can be controlled by connecting the drain and collector electrodes to one main terminal for the device with a resistor between either the drain region/drift region interface or the collector junction and the main terminal of the device.

摘要翻译： IGBT和FET集成在公共半导体主体中，并共享源极/发射极，基极和漂移区域以及绝缘栅电极。 该器件的导通电阻和关断时间可以通过将漏极和集电极连接到一个主端子来控制，该主端子在漏区/漂移区界面或集电极结之间的电阻器与主端子之间 装置。

公开(公告)号：US4333965A

公开(公告)日：1982-06-08

申请号：US187501

申请日：1980-09-15

申请人： Tat-Sing P. Chow ,  Mario Ghezzo

发明人： Tat-Sing P. Chow ,  Mario Ghezzo

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  B05D5/12 ,  H01L21/306

CPC分类号： H01L21/308 ,  H01L21/3081 ,  H01L21/32 ,  H01L21/76205 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/114 ,  Y10S148/117

摘要： A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed. Mesas, the tops of which are the active regions, are formed by ion beam etching of the silicon substrate. The mesas are protected by caps of silicon nitride overlying the top and sides of the mesas during field oxide formation. Subsequently the caps of silicon nitride are removed and the exposed sides of the mesas are oxidized to form a thick layer of silicon dioxide contiguous to the mesas.

摘要翻译： 一种在其中将形成集成电路元件的硅衬底的有源区附近减小横向场氧化的方法。 其顶部是有源区的Mesas通过硅衬底的离子束蚀刻形成。 在场氧化物形成期间，台面由位于台面顶部和侧面的氮化硅覆盖物保护。 随后，去除氮化硅的盖，并且台面的暴露的侧面被氧化以形成与台面相邻的厚的二氧化硅层。

公开(公告)号：US4429011A

公开(公告)日：1984-01-31

申请号：US362682

申请日：1982-03-29

申请人： Manjin J. Kim ,  Tat-Sing P. Chow

发明人： Manjin J. Kim ,  Tat-Sing P. Chow

IPC分类号： C23C8/24 ,  H01L21/28 ,  H01L21/318 ,  H01L21/321 ,  B05D5/12 ,  H01L21/306

CPC分类号： H01L21/28079 ,  C23C8/24 ,  H01L21/28105 ,  H01L21/318 ,  H01L21/321

摘要： A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of ammonia in the range from about 400.degree. C. to 850.degree. C. for a time to cause the atmosphere to react with the conductor to convert a portion of the conductor into molybdenum nitride.

摘要翻译： 描述了一种复合导电结构，其包括绝缘基板，其上设置有由氮化钼层覆盖的钼的导体以及制造该结构的方法。 该方法包括在约400℃至850℃的氨气氛中加热钼导体一段时间，使气氛与导体反应，将一部分导体转变为氮化钼。

公开(公告)号：US4862242A

公开(公告)日：1989-08-29

申请号：US807612

申请日：1985-12-11

申请人： Eric J. Wildi ,  Tat-Sing P. Chow

发明人： Eric J. Wildi ,  Tat-Sing P. Chow

IPC分类号： H01L21/761

CPC分类号： H01L21/761

摘要： A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device can accordingly be operated at high voltage with respect to the wafer substrate. The isolation structure in one form of the wafer comprises an N+ high voltage tub included in the wafer and a P+ ground region situated in the expitaxial layer, adjoining the substrate, and horizontally circumscribing the N+ high voltage tub and being spaced therefrom by a minimum layer extent of a portion of the epitaxial layer that is of N conductivity type. The N+ high voltage tub comprises an N+ high voltage region situated in the epitaxial layer and surrounding a device region in which the semiconductor device is at least partially contained and, further, an N+ buried layer underlying the N+ high voltage region and the entirety of the device region.

摘要翻译： 具有其上具有外延层的衬底的半导体晶片包括与衬底以及通过包括半导体材料的电隔离结构与晶片中的任何其它器件电隔离的半导体器件。 因此，相对于晶片衬底，半导体器件可以以高电压工作。 晶片的一种形式的隔离结构包括晶片中包括的N +高压电池和位于外延层中的毗邻衬底的P +接地区域，并且水平地围绕N +高压电池并与其隔开最小层 具有N导电类型的外延层的一部分的程度。 N +高压槽包括位于外延层中的N +高电压区域，并且围绕其中至少部分地包含半导体器件的器件区域，并且还包括在N +高电压区域下面的N +掩埋层和整个 设备区域。

公开(公告)号：US5510281A

公开(公告)日：1996-04-23

申请号：US406440

申请日：1995-03-20

申请人： Mario Ghezzo ,  Tat-Sing P. Chow ,  James W. Kretchmer ,  Richard J. Saia ,  William A. Hennessy

发明人： Mario Ghezzo ,  Tat-Sing P. Chow ,  James W. Kretchmer ,  Richard J. Saia ,  William A. Hennessy

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/1608 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802

摘要： A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconductor layer; and patterning the gate electrode layer to form a gate electrode portion adjacent to an edge of the patterned refractory dielectric layer. Preferably the step of conformally depositing the gate electrode layer includes depositing an electrically conductive layer having the same thickness as a combined width of the first and second spacers. In one embodiment the semiconductor layer includes silicon carbide, the patterned refractory dielectric layer includes silicon dioxide, the spacers include silicon nitride, and the gate electrode layer includes polysilicon.

摘要翻译： 一种用于制造半导体器件的方法包括在第一导电类型的半导体层上图形化难熔电介质层; 在图案化的难熔电介质层和半导体层上共形沉积第一间隔层; 图案化第一间隔层以留下邻近图案化耐火介电层的边缘的第一间隔物; 注入第二导电类型的离子以在半导体层中形成基极区; 在图案化的耐火介电层和半导体层上共形沉积第二间隔层; 图案化第二间隔层以留下与第一间隔物的边缘相邻的第二间隔物; 注入第一导电类型的离子以在基区中形成源区; 去除所述第一和第二间隔件; 在所述半导体层的至少一部分上施加栅极绝缘体层; 在所述栅极绝缘体层和所述半导体层上共形沉积栅电极层; 以及图案化栅极电极层以形成邻近图案化耐火介电层的边缘的栅电极部分。 优选地，共形沉积栅极电极层的步骤包括沉积具有与第一和第二间隔物的组合宽度相同的厚度的导电层。 在一个实施例中，半导体层包括碳化硅，图案化的难熔电介质层包括二氧化硅，间隔物包括氮化硅，并且栅电极层包括多晶硅。