公开(公告)号：US06702648B1

公开(公告)日：2004-03-09

申请号：US10277559

申请日：2002-10-22

申请人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： B24B4900

CPC分类号： B24B37/013 ,  B24B49/12

摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.

摘要翻译： 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。

公开(公告)号：US06684172B1

公开(公告)日：2004-01-27

申请号：US10034165

申请日：2001-12-27

申请人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

发明人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

IPC分类号： G01L2500

CPC分类号： C23C16/52 ,  C23C14/547 ,  C23C18/1675 ,  C25D21/12 ,  H01L21/76877

摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.

摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。

公开(公告)号：US06673524B2

公开(公告)日：2004-01-06

申请号：US09780275

申请日：2001-02-09

申请人： Kouros Ghandehari ,  Bruno LaFontaine ,  Bhanwar Singh

发明人： Kouros Ghandehari ,  Bruno LaFontaine ,  Bhanwar Singh

IPC分类号： C08J718

CPC分类号： G03F1/32 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/26 ,  G03F1/30 ,  G03F1/68

摘要： An exemplary method of forming an attenuating extreme ultraviolet (EUV) phase-shifting mask is described. This method can include providing a multi-layer mirror over an integrated circuit substrate or a mask blank, providing a buffer layer over the multi-layer mirror, providing a dual element material layer over the buffer layer, and selectively growing features on the integrated circuit substrate or mask blank using a photon assisted chemical vapor deposition (CVD) process when depositing the dual element layer.

摘要翻译： 描述形成衰减极紫外（EUV）移相掩模的示例性方法。 该方法可以包括在集成电路衬底或掩模板上提供多层反射镜，在多层反射镜上提供缓冲层，在缓冲层上提供双重元件材料层，以及在集成电路上选择性地增长特征 衬底或掩模坯料，当沉积双重元件层时，使用光子辅助化学气相沉积（CVD）工艺。

公开(公告)号：US06665065B1

公开(公告)日：2003-12-16

申请号：US09829195

申请日：2001-04-09

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Wolfram Porsche

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Wolfram Porsche

IPC分类号： G01N2100

CPC分类号： G01N21/95692

摘要： A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.

摘要翻译： 提供了用于检测掩模或掩模版中的潜在缺陷的系统和方法，该缺陷可以随曝光波长的辐射而变化。 作为示例，检查掩模或掩模版，暴露于指定波长的辐射，然后再检查。 暴露前后的检查结果之间的相关性提供暴露相关缺陷的指示，其可以包括由暴露引起的缺陷生长和/或形成缺陷。 为了进一步说明，掩模或掩模版的检查和曝光的组合可以相对于薄膜掩模或掩模版实现，以便检测与使用掩模或掩模版的防护薄膜相关的附加缺陷。

公开(公告)号：US06594024B1

公开(公告)日：2003-07-15

申请号：US09886863

申请日：2001-06-21

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Carmen Morales

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Carmen Morales

IPC分类号： G01B1128

CPC分类号： B24B37/005 ,  B24B49/12 ,  G01N21/47 ,  G01N21/9501 ,  H01L21/30625

摘要： One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.

摘要翻译： 本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统，以便确定包括晶片的CMP工艺端点，其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库，以确定晶片的状态。 另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法，其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。

公开(公告)号：US06559446B1

公开(公告)日：2003-05-06

申请号：US09670775

申请日：2000-09-27

申请人： Bryan K. Choo ,  Bhanwar Singh

发明人： Bryan K. Choo ,  Bhanwar Singh

IPC分类号： G01N23225

CPC分类号： G01N23/225

摘要： A system and method are disclosed for measuring and/or imaging a feature having a re-entrant cross-sectional profile. Beams are emitted onto the feature and substrate at different angles during corresponding measurement intervals. An feature data set of the feature is characterized for each measurement interval. The data associated with each measurement interval are aggregated to provide a cross-sectional representation of the having dimensions proportional to the feature. As a result, a more accurate feature profile may be determined, including a cross-sectional dimension of the re-entrant feature at the juncture between the feature and substrate.

摘要翻译： 公开了一种用于测量和/或成像具有重入横截面轮廓的特征的系统和方法。 光束在相应的测量间隔内以不同的角度发射到特征和基底上。 特征的特征数据集的特征在于每个测量间隔。 与每个测量间隔相关联的数据被聚合以提供具有与特征成比例的尺寸的横截面表示。 结果，可以确定更准确的特征轮廓，包括在特征和基底之间的交界处的入侵特征的横截面尺寸。

公开(公告)号：US06455332B1

公开(公告)日：2002-09-24

申请号：US09564406

申请日：2000-05-01

申请人： Bhanwar Singh ,  Michael Templeton

发明人： Bhanwar Singh ,  Michael Templeton

IPC分类号： H01L2100

CPC分类号： H01L22/34

摘要： A method of making and using a reference wafer and a metrology system to calibrate tools in a photolithographic system. The reference wafer includes a silicon substrate, a dielectric or insulating layer disposed above the silicon substrate and a pattern disposed above the insulating layer. The pattern is coupled to the silicon substrate and the silicon substrate acts as a ground for the pattern. As a result, charge buildup on the pattern is mitigated since excess charge is dissipated into the silicon substrate.

摘要翻译： 制造和使用参考晶片和计量系统来校准光刻系统中的工具的方法。 参考晶片包括硅衬底，设置在硅衬底上方的电介质层或绝缘层以及设置在绝缘层之上的图案。 该图案耦合到硅衬底，并且硅衬底用作图案的接地。 结果，由于过量的电荷消散到硅衬底中，因此减轻了图案上的电荷积累。

公开(公告)号：US06448097B1

公开(公告)日：2002-09-10

申请号：US09911236

申请日：2001-07-23

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： H01L3126

CPC分类号： G01N21/64 ,  G01N2021/6417 ,  H01L22/26

摘要： A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.

摘要翻译： 提供了一种使用荧光光谱法确定和控制半导体衬底的开发的系统和方法。 本发明的一个方面涉及使用荧光光谱学来促进在光致抗蚀剂材料层的显影期间控制化学修剪蚀刻工艺的系统和方法。 化学修剪蚀刻工艺包括将修剪化合物或材料施加到图案化的光致抗蚀剂上。 修整组合物或材料可扩散到图案化抗蚀剂的侧面和顶部。 抗蚀剂的扩散区域可溶于显影剂，这有助于在图案化的光致抗蚀剂中产生更小的特征。 荧光光谱系统可用于测量孤立和致密的光栅或CD，并使用CD的演变来确定何时终止化学修饰过程。

公开(公告)号：US06441349B1

公开(公告)日：2002-08-27

申请号：US09558643

申请日：2000-04-26

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur

IPC分类号： H05B368

CPC分类号： H01L21/67103

摘要： A system and method for facilitating uniform heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material. The system can include at least one heating element and a heat transfer fluid, the heating element heating the heat transfer fluid, which in turn heats the material. The transfer fluid more evenly distributes the heat from the heating element, which can have hot and cold spots at the material.

摘要翻译： 提供了一种用于促进材料的均匀加热温度的系统和方法。 该材料可以是光致抗蚀剂，顶部或底部抗反射涂层，低K电介质材料，SOG或其它旋涂材料。 该系统可以包括至少一个加热元件和传热流体，该加热元件加热该传热流体，该热传导流体依次加热该材料。 传输流体更均匀地分配来自加热元件的热​​量，其可以在材料上具有热点和冷点。

公开(公告)号：US06322009B1

公开(公告)日：2001-11-27

申请号：US09429992

申请日：1999-10-29

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： B05B900

CPC分类号： H01L21/6708 ,  H01L21/67051

摘要： A combination nozzle for applying a developer material and a washing solution material at different time intervals to a photoresist material layer disposed on a wafer is provided. The combination nozzle includes a number of developer nozzle tips connected to a developer supply line and a number of washing solution nozzle tips connected to a washing solution supply line. The developer supply line and the washing solution supply line ensure that the developer material and the washing solution material are always substantially isolated from one another. Furthermore, the developer nozzle tips and the washing solution nozzle tips are arranged so that developer material and washing solution material do not come into contact with one another. The volume of the material and the volume flow of the material can be controlled by electronically controlled valves.

摘要翻译： 提供了用于将显影剂材料和洗涤液材料以不同的时间间隔施加到设置在晶片上的光致抗蚀剂材料层的组合喷嘴。 组合喷嘴包括连接到显影剂供应管线的多个显影剂喷嘴尖端和连接到洗涤溶液供应管线的多个洗涤溶液喷嘴尖端。 显影剂供应管线和洗涤溶液供应管线确保显影剂材料和洗涤液材料总是基本上彼此隔离。 此外，显影剂喷嘴尖端和洗涤溶液喷嘴尖端被布置成使得显影剂材料和洗涤液材料彼此不接触。 材料的体积和材料的体积流量可以通过电子控制阀来控制。