公开(公告)号：US20070184996A1

公开(公告)日：2007-08-09

申请号：US11307394

申请日：2006-02-06

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Mei-Chi Wang ,  Jiunn-Hsiung Liao ,  Wei-Cheng Yang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Mei-Chi Wang ,  Jiunn-Hsiung Liao ,  Wei-Cheng Yang

IPC分类号： C11D7/32

CPC分类号： C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76814

摘要： A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.

摘要翻译： 描述了在等离子体处理之后留下残留物的方法。 首先，提供至少具有材料层的基板。 材料层包括金属。 然后，进行含氟等离子体处理，使得在材料层的表面上形成含有上述金属材料的残渣。 之后，使用清洁剂进行湿式清洗操作以除去残留物。 清洗剂是含有水，稀释的氢氟酸和酸溶液的溶液。

公开(公告)号：US08952392B2

公开(公告)日：2015-02-10

申请号：US13369260

申请日：2012-02-08

申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

IPC分类号： H01L29/15 ,  H01L21/336

CPC分类号： H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

摘要翻译： 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US08592322B2

公开(公告)日：2013-11-26

申请号：US13535370

申请日：2012-06-28

申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

摘要翻译： 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

公开(公告)号：US08524608B1

公开(公告)日：2013-09-03

申请号：US13456245

申请日：2012-04-26

申请人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Meng-Chun Lee

发明人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Meng-Chun Lee

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/32139

摘要： The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.

摘要翻译： 本发明提供一种在半导体器件中制造图案化结构的方法，其包括以下处理。 首先，在基板上依次形成目标层，第一掩模和第一图案化掩模。 然后，执行第一蚀刻工艺以在衬底上形成多个特征结构，其中每个特征结构包括图案化的第一掩模和图案化目标层。 第二图案化掩模形成在衬底上，其中第二图案化掩模覆盖特征结构的一部分并暴露预定区域。 执行第二蚀刻处理以完全消除预定区域内的特征结构。 最后，执行第三蚀刻处理以完全消除未被图案化的第一掩模覆盖的目标层。

公开(公告)号：US08461649B2

公开(公告)日：2013-06-11

申请号：US13234159

申请日：2011-09-16

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

摘要翻译： 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

公开(公告)号：US20120313178A1

公开(公告)日：2012-12-13

申请号：US13158479

申请日：2011-06-13

申请人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

发明人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC分类号： H01L21/3205 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

摘要翻译： 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08310012B2

公开(公告)日：2012-11-13

申请号：US12759670

申请日：2010-04-13

申请人： Guang-Yaw Hwang ,  Yu-Ru Yang ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

发明人： Guang-Yaw Hwang ,  Yu-Ru Yang ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的栅极电介质层和形成在栅极介电层上的至少第一导电型金属栅极。 第一导电型金属栅极包括在填充金属层和栅极介电层之间形成的填充金属层和U型金属层。 U型金属层的最上部比填充金属层低。

公开(公告)号：US20120270403A1

公开(公告)日：2012-10-25

申请号：US13535370

申请日：2012-06-28

申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC分类号： H01L21/306

CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

摘要翻译： 公开了一种制造开口的方法。 首先，提供其上具有自对准硅化物区域的半导体衬底。 蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。 其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。 然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。 然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

公开(公告)号：US08293639B2

公开(公告)日：2012-10-23

申请号：US12371809

申请日：2009-02-16

申请人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/76895

摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

摘要翻译： 描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。 在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。 执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。 执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。 控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US08168374B2

公开(公告)日：2012-05-01

申请号：US12854913

申请日：2010-08-12

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： G03F7/26

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

摘要翻译： 提供一种形成接触孔的方法。 在光致抗蚀剂层中形成图案。 将图案交换成硅光致抗蚀剂层以形成第一开口。 在另一光致抗蚀剂层中形成另一图案。 将图案交换为硅光致抗蚀剂层以形成第二开口。 将具有第一和第二开口的图案交换到层间电介质层和蚀刻停止层以形成接触孔。 本发明具有两次曝光工艺和两次蚀刻工艺以形成具有小距离的接触孔。