Weighted erasure codec for the (24, 12) extended Golay code
    84.
    发明授权
    Weighted erasure codec for the (24, 12) extended Golay code 失效
    加权擦除编解码器(24,12)扩展格莱码

    公开(公告)号:US4397022A

    公开(公告)日:1983-08-02

    申请号:US230136

    申请日:1981-01-30

    IPC分类号: H03M13/15 G06F11/10

    CPC分类号: H03M13/15

    摘要: A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.

    摘要翻译: 编解码器由编码器和解码器组成。 编码器提供12个信息位,根据用于(23,12)Golay码的多项式生成的11个奇偶校验位,以及在选择的发送时间到发射机的总体奇偶校验位,以形成24位数据块。 解码器分为两个独立的列表解码器,比较器和公共时钟发生器和输出缓冲器。 每个列表解码器被分为校正子生成器和整体奇偶校验生成器,校正子错误模式表,输入缓冲器,纠错逻辑和四错误检测逻辑。 错误模式表包括一对只读存储器,其存储每个对应于每个综合征的每个ROM地址中最可能的12位错误模式。 附加的4位输出用于指示相关错误模式中的错误数量。 比较器比较两个独立解码器中检测到的错误数,并选择具有较少错误数量的解码器来提供校正数据。

    Tracking Non-Geo Synchronous Orbit satellites on orbiting planes of regular motion patterns

    公开(公告)号:US11947023B2

    公开(公告)日:2024-04-02

    申请号:US17245301

    申请日:2021-04-30

    IPC分类号: G01S19/42 G01S19/14 H01Q3/02

    CPC分类号: G01S19/42 G01S19/14 H01Q3/02

    摘要: A system and method for tracking non-geo synchronous orbit satellites on orbiting planes of regular motion patterns. The method includes providing a first satellites moving in a direction descending in latitude in first orbital planes and a second satellites moving in a direction ascending in latitude in second orbital planes; steering an antenna to an antenna tilt φ from normal with a single axis mechanism lined up with a first axis; scanning, electronically, with a linear array at a scan angle ψ along a second axis; and locking to a signal from a handed-from satellite from the first satellites, where the first axis is angled from the second axis, the steering along the first axis and the scanning along the second axis jointly track the handed-from satellite, the first orbits seem parallel, the second orbits seem parallel, and the first orbits seem aligned with the antenna tilt φ. A handoff between the first satellites may use one of the second satellites as a steppingstone.

    Method and apparatus for a parameterized interleaver design process
    86.
    发明授权
    Method and apparatus for a parameterized interleaver design process 有权
    用于参数化交织器设计过程的方法和装置

    公开(公告)号:US08527833B2

    公开(公告)日:2013-09-03

    申请号:US13231474

    申请日:2011-09-13

    IPC分类号: H03M13/00

    摘要: A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

    摘要翻译: 提供了一种参数化的交织器设计过程,其优化了任何尺寸的交织器的设计,并且可以仅使用少量设计参数来完全指定。 根据参数化交织器设计处理,生成长度为N的交织器pi(i)。 定义了多个子鉴别掩码,并且将第一中间交织器置换分割成多个子组,其中子组的数量对应于子鉴别掩码的数量。 第一中间交织器排列的每个子组被划分成多个其他子组,并且每个子质量掩模被应用于第一中间交织器排列的相应子组的其他子组中的每一个,导致相应部分 第二中间交织器排列。 至少部分地基于第一和第二中间交织器排列来生成所产生的交织器pi(i)。

    Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels
    87.
    发明授权
    Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels 有权
    用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进

    公开(公告)号:US08392793B2

    公开(公告)日:2013-03-05

    申请号:US12753528

    申请日:2010-04-02

    IPC分类号: H03M13/00

    摘要: Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.

    摘要翻译: 方法包括配置M并行累积引擎,使用累积引擎在第一组特定奇偶校验位地址处累积第一信息位,将第一组特定奇偶校验位地址的每个成员的奇偶校验位地址增加预定的偏移量 对于每个新的信息位,在与特定奇偶校验位地址相偏移的奇偶校验位地址处累积后续信息比特,直到达到M + 1个信息比特为止,将下一个M个信息比特累加在第二组 使用累积引擎的特定奇偶校验位地址,增加第二组特定奇偶校验位地址的每个成员的奇偶校验位地址每个新信息比特的预定偏移量; 并重复累积和增加地址直到信息位耗尽。 描述相关系统。

    SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES
    88.
    发明申请
    SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES 有权
    卫星通信系统利用低密度奇偶校验码

    公开(公告)号:US20120221915A1

    公开(公告)日:2012-08-30

    申请号:US13408953

    申请日:2012-02-29

    IPC分类号: H03M13/05 G06F11/10

    摘要: An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.

    摘要翻译: 公开了一种用于通过卫星可靠地通信以支持包括例如直接广播卫星和数据服务在内的通信服务的方法。 编码输入消息,产生结构化的低密度奇偶校验(LDPC)编码消息。 编码消息根据高阶调制方案进行调制,该高阶调制方案具有每个信令点(例如8-PSK(相移键控)和16-QAM(正交幅度调制))多于两个符号的信号星座。 该系统包括被配置成通过卫星传播调制信号的发射机。 上述方法特别适用于需要高数据速率的带宽受限通信系统。

    Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications
    89.
    发明授权
    Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications 有权
    提供支持宽带卫星应用的短块长度低密度奇偶校验(LDPC)码的方法和系统

    公开(公告)号:US08181085B2

    公开(公告)日:2012-05-15

    申请号:US12943613

    申请日:2010-11-10

    IPC分类号: H03M13/00

    摘要: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

    摘要翻译: 提供了一种用于编码短帧长度低密度奇偶校验(LDPC)码的方法。 编码器生成具有外部Bose Chaudhuri Hocquenghem(BCH)码的LDPC码。 通过将奇偶校验矩阵的部分部分限制为三角形和/或满足其他要求,使得解码器的位节点和校验节点之间的通信被简化,对LDPC码施加结构。 此外,循环冗余校验(CRC)编码器被提供以根据CRC码对输入信号进行编码。 这种方法在卫星数字视频广播业务中具有特殊应用。