公开(公告)号：US07132896B2

公开(公告)日：2006-11-07

申请号：US10981155

申请日：2004-11-04

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L7/093 ,  H03L7/095 ,  H03B1/04

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/095

摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.

摘要翻译： 提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。 在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。 为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。 充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

公开(公告)号：US07113881B2

公开(公告)日：2006-09-26

申请号：US10981157

申请日：2004-11-04

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R27/28 ,  G01R31/26

CPC分类号： G01R31/2632

摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.

摘要翻译： 提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。 传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。 通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。 因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

公开(公告)号：US08381143B2

公开(公告)日：2013-02-19

申请号：US13014828

申请日：2011-01-27

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

摘要翻译： 提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时， 输入信号通过线性电阻器路由。 线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。 线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。 线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

公开(公告)号：US08086989B2

公开(公告)日：2011-12-27

申请号：US12174572

申请日：2008-07-16

申请人： Eskinder Hailu ,  Takeo Yasuda

发明人： Eskinder Hailu ,  Takeo Yasuda

IPC分类号： G06F17/50

CPC分类号： G06F17/5059 ,  G06F2217/84

摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.

摘要翻译： 用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。 该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。 异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。 每个同步组包括用于同步时钟源的多个HFGC块。 该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。 属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是 第二输入时钟信号。

公开(公告)号：US07786813B2

公开(公告)日：2010-08-31

申请号：US12098490

申请日：2008-04-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

公开(公告)号：US07782146B2

公开(公告)日：2010-08-24

申请号：US12098483

申请日：2008-04-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

摘要翻译： 公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与 一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。 每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

公开(公告)号：US20090326862A1

公开(公告)日：2009-12-31

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00 ,  H03L7/06

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

公开(公告)号：US20090164957A1

公开(公告)日：2009-06-25

申请号：US12174572

申请日：2008-07-16

申请人： Eskinder Hailu ,  Takeo Yasuda

发明人： Eskinder Hailu ,  Takeo Yasuda

IPC分类号： G06F17/50

CPC分类号： G06F17/5059 ,  G06F2217/84

摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.

摘要翻译： 用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。 该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。 异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。 每个同步组包括用于同步时钟源的多个HFGC块。 该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。 属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是 第二输入时钟信号。

公开(公告)号：US20090146743A1

公开(公告)日：2009-06-11

申请号：US11952706

申请日：2007-12-07

申请人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L7/085 ,  H03L7/08

CPC分类号： H03L7/08

摘要： Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

摘要翻译： 用于确定锁相环电路（PLL）中的压控振荡器（VCO）线性度，占空比确定和占空比校正的系统和方法一个实施例包括一种方法，包括以下步骤：将PLL的VCO的频率响应确定为 占空比的功能，将基于VCO输出的信号施加到VCO输入，测量VCO输出信号的最终频率，确定对应于测量频率的占空比，以及配置占空比校正单元校正占空比 的VCO输出信号约为50％。 确定VCO的频率响应可以包括对于0％和100％之间的几个不同占空比值的每一个，将VCO输入信号施加到VCO并确定VCO输出信号的对应频率。 这也可以在0％和100％的占空比下完成。

公开(公告)号：US20090128206A1

公开(公告)日：2009-05-21

申请号：US11942983

申请日：2007-11-20

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03K5/04 ,  H03L7/099

CPC分类号： H03K3/017 ,  H03L7/0995

摘要： An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

摘要翻译： 提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的装置和方法。 说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。 一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。 因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。 结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。