公开(公告)号：US06470478B1

公开(公告)日：2002-10-22

申请号：US09345163

申请日：1999-06-29

申请人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G06F17/5022

摘要： A method and system that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, a counting instrument is described utilizing the same hardware description language. The counting instrument is designed to detect occurrences of a count event within the design entity during simulation of the digital circuit design. The counting instrument is associated with the design entity utilizing a non-conventional call, such that the counting instrument may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design. In association with the counting instrument, a linear feedback shift register is automatically generated for recording the number of occurrences of the count event within the design entity.

摘要翻译： 一种利用硬件描述语言表达的方法和系统，用于在模拟期间高效全面地监测数字电路设计的性能特征。 根据本发明，首先使用硬件描述语言描述作为数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述计数仪器。 计数仪器被设计为在模拟数字电路设计期间检测设计实体内的计数事件的发生。 计数仪器与设计实体相关联，利用非传统调用，使得计数仪器可用于监视模拟模型内的设计实体的每个实例化，而不需要将仪器实体纳入数字电路设计。 与计数仪器相关联，自动生成线性反馈移位寄存器，用于记录设计实体内计数事件的发生次数。

公开(公告)号：US08809902B2

公开(公告)日：2014-08-19

申请号：US13274411

申请日：2011-10-17

申请人： Holger Huesken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Roesner

发明人： Holger Huesken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Roesner

IPC分类号： H01L29/739

CPC分类号： H01L29/0688 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/872

摘要： A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

摘要翻译： 提供功率半导体二极管。 功率半导体二极管包括具有第一导电类型的第一发射极区域，第二导电类型的第二发射极区域和布置在第一发射极区域和第二发射极区域之间的第一导电类型的漂移区域的半导体衬底。 漂移区域与第二发射极区域形成pn结。 第一发射极金属化与第一发射极区域接触。 第一发射极区域包括第一导电类型的第一掺杂区域和第一导电类型的第二掺杂区域。 第一掺杂区与第一发射极金属化形成欧姆接触，第二掺杂区与第一发射极金属化形成非欧姆接触。 第二发射极金属化与第二发射极区域接触。

公开(公告)号：US08028273B2

公开(公告)日：2011-09-27

申请号：US12106053

申请日：2008-04-18

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F9/44 ,  G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital design. In addition, a clone latch is specified within the digital design utilizing an HDL clone latch declaration. An HDL attribute-value pair is associated with the HDL clone latch declaration to indicate a relationship between the clone latch and the parent latch according to which the clone latch is automatically set to a same value as the parent latch when the parent latch is set. Thereafter, when a configuration compiler receives one or more design intermediate files containing the clone latch declaration, the configuration compiler creates at least one data structure in a configuration database representing the clone latch and the relationship between the clone latch and the parent latch.

摘要翻译： 公开了支持在数字设计中插入克隆锁存器的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的父锁存器在表示数字设计的HDL文件之一中的HDL语句中被指定。 此外，使用HDL克隆锁存器声明在数字设计中指定克隆锁存器。 HDL属性值对与HDL克隆锁存器声明相关联，以指示克隆锁存器和父锁存器之间的关系，根据该关系，克隆锁存器在父锁存器被置位时自动设置为与父锁存器相同的值。 此后，当配置编译器接收到包含克隆锁存器声明的一个或多个设计中间文件时，配置编译器在表示克隆锁存器的配置数据库中创建至少一个数据结构以及克隆锁存器和父锁存器之间的关系。

公开(公告)号：US07711537B2

公开(公告)日：2010-05-04

申请号：US11381437

申请日：2006-05-03

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.

摘要翻译： 根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。 响应于数据集的接收，处理数据集中的条目以识别信号组名称。 与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。 然后将与多个信号的实例相关联的事件跟踪文件的仿真结果包含在仿真结果的呈现中。

公开(公告)号：US07700427B2

公开(公告)日：2010-04-20

申请号：US11762582

申请日：2007-06-13

申请人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

发明人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L25/0657 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66818 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.

摘要翻译： 本发明的实施例一般涉及用于制造集成电路的方法，用于制造单元布置的方法，集成电路，单元布置和存储器模块。 在本发明的一个实施例中，提供一种用于制造具有单元布置的集成电路的方法，包括形成至少一个半导体鳍结构，其具有用于多个鳍场效应晶体管的面积，其中每个鳍场效应晶体管的面积 包括具有第一鳍结构宽度的第一区域，具有第二鳍结构宽度的第二区域，其中第二鳍结构宽度小于第一鳍结构宽度。 此外，在半导体鳍片结构的第二区域上或上方形成多个电荷存储区域。

公开(公告)号：US07617085B2

公开(公告)日：2009-11-10

申请号：US12129813

申请日：2008-05-30

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.

摘要翻译： 根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。 响应于数据集的接收，处理数据集中的条目以识别信号组名称。 与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。 然后将与多个信号的实例相关联的事件跟踪文件的仿真结果包含在仿真结果的呈现中。

公开(公告)号：US07560351B2

公开(公告)日：2009-07-14

申请号：US11324803

申请日：2006-01-03

申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/78 ,  Y10S438/964

摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

摘要翻译： 提出了一种集成电路布置和制造方法。 集成电路装置包含半导体和金属电极。 使用延伸穿过半导体和电极之间的过渡层的半导体和/或电极的部分区域，增加半导体和电极之间的接触面积而不增加横向尺寸。

公开(公告)号：US07529655B2

公开(公告)日：2009-05-05

申请号：US12106416

申请日：2008-04-21

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

公开(公告)号：US07528425B2

公开(公告)日：2009-05-05

申请号：US11193026

申请日：2005-07-29

申请人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

发明人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  G11C16/0475 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7923

摘要： A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate (1), a second doping region (7) disposed in the substrate (1), a channel region (22) disposed in the substrate (1) between the first doping region (6) and the second doping region (7), a charge-trapping layer stack (2) disposed on the substrate (1), on the channel region (22), on a portion of the first doping region (6) and on a portion of the second doping region (7). Each memory cell (21-1) further comprises a conductive layer (3) disposed on the charge-trapping layer stack (2), wherein the conductive layer (3) is electrically floating. A dielectric layer (4) is disposed on a top surface of the conductive layer (3) and on sidewalls (23) of the conductive layer (3). The first line (15-1) extends along a first direction and is coupled to the first doping region (6), and the second line (15-2; 16-1) extends along the first direction and is coupled to the second doping region (7). The at least one wordline (5-1) extends along a second direction and is disposed on the dielectric layer (4).

摘要翻译： 一种具有多个存储单元（21-1）的半导体存储器，所述半导体存储器具有衬底（1），至少一个字线（5-1），第一（15-1）和第二线（15-2） ; 16-1），其中多个存储单元（21-1）中的每一个包括设置在所述基板（1）中的第一掺杂区域（6），设置在所述基板（1）中的第二掺杂区域（7） 设置在第一掺杂区域（6）和第二掺杂区域（7）之间的衬底（1）中的沟道区域（22），设置在衬底（1）上的电荷捕获层堆叠（2） 在第一掺杂区域（6）的一部分上和第二掺杂区域（7）的一部分上的区域（22）。 每个存储单元（21-1）还包括设置在电荷捕获层堆叠（2）上的导电层（3），其中导电层（3）是电浮置的。 介电层（4）设置在导电层（3）的顶表面和导电层（3）的侧壁（23）上。 第一行（15-1）沿着第一方向延伸并且耦合到第一掺杂区域（6），并且第二线路（15-2; 16-1）沿第一方向延伸并耦合到第二掺杂区域 地区（7）。 所述至少一个字线（5-1）沿着第二方向延伸并设置在所述电介质层（4）上。

公开(公告)号：US20080294413A1

公开(公告)日：2008-11-27

申请号：US12130104

申请日：2008-05-30

申请人： GABOR BOBOK ,  Wolfgang Roesner ,  Derek E. Williams

发明人： GABOR BOBOK ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。