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    Method for producing a substrate
    2.
    发明授权
    Method for producing a substrate 有权
    制造基板的方法

    公开(公告)号：US07611928B2

    公开(公告)日：2009-11-03

    申请号：US10968846

    申请日：2004-10-18

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76254

    摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

    摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。

    Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration
    3.
    发明授权
    Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效
    具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度

    公开(公告)号：US07598543B2

    公开(公告)日：2009-10-06

    申请号：US11438883

    申请日：2006-05-23

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

    摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

    High-density NROM-FINFET
    4.
    发明授权
    High-density NROM-FINFET 失效
    高密度NROM-FINFET

    公开(公告)号：US07208794B2

    公开(公告)日：2007-04-24

    申请号：US11073017

    申请日：2005-03-04

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

    摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

    摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

    Method for the production of a memory cell, memory cell and memory cell arrangement
    6.
    发明授权
    Method for the production of a memory cell, memory cell and memory cell arrangement 有权
    用于生产存储器单元，存储单元和存储单元布置的方法

    公开(公告)号：US07195978B2

    公开(公告)日：2007-03-27

    申请号：US10999810

    申请日：2004-11-29

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Michael Specht

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Michael Specht

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located essentially in a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, a channel region located between the two source/drain regions, wherein the channel region at least partly laterally overlaps the floating gate and the read gate electrode.

    摘要翻译： 具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极， 基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个 源极/漏极区域基本上位于辅助衬底的不含第二栅极绝缘层和读取栅电极的剩余材料的表面区域中，位于两个源极/漏极区域之间的沟道区域，其中沟道区域在 至少部分地侧向重叠浮置栅极和读取栅电极。

    Semiconductor memory with vertical memory transistors and method for fabricating it
    8.
    发明授权
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US07265413B2

    公开(公告)日：2007-09-04

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

    Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor
    10.
    发明授权
    Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor 有权
    用于制造层布置的方法以及用作双栅极场效应晶体管的层布置

    公开(公告)号：US07312126B2

    公开(公告)日：2007-12-25

    申请号：US11178251

    申请日：2005-07-08

    申请人： Gurkan Ilicali ,  Richard Johannes Luyken ,  Wolfgang Roesner

    发明人： Gurkan Ilicali ,  Richard Johannes Luyken ,  Wolfgang Roesner

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6656 ,  H01L29/66484 ,  H01L29/7831

    摘要： The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is formed on the sacrificial layer, a first electrically insulating layer is formed on the first semiconductor layer, an electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned, the first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer, a substrate is secured over the patterned electrically conductive layer, material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.

    摘要翻译： 一种制造层布置的方法，该层布置允许形成双栅场效应晶体管。 在该方法中，在辅助基板上形成多孔硅层作为牺牲层。 在牺牲层上形成第一半导体层，在第一半导体层上形成第一电绝缘层。 在第一电绝缘层上形成导电层，该导电层被横向图案化。 使用横向图案化的导电层作为掩模，共同地横向图案化第一电绝缘层，牺牲层和第一半导体层。 此外，半导体结构邻近图案化牺牲层和图案化的第一半导体层的侧壁形成。 将衬底固定在图案化的导电层上，并且去除辅助衬底的材料，使得牺牲层未被覆盖。 此外，选择性地去除牺牲层以形成沟槽，并且在沟槽中形成第二电绝缘层，然后在该第二电绝缘层上形成导电结构。