公开(公告)号：US5885761A

公开(公告)日：1999-03-23

申请号：US780705

申请日：1997-01-08

申请人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

发明人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/417 ,  H01L21/22 ,  H01L21/38 ,  H01L21/4763

CPC分类号： H01L29/66575 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6659 ,  H01L21/2257 ,  H01L29/665

摘要： A semiconductor device and process for manufacture thereof is disclosed in which an elevated, active polysilicon region is formed by forming a gate electrode/nitride layer structure on a surface of a semiconductor substrate with spacers formed on adjacent walls to define an active region of the substrate. A thick polysilicon layer is formed over the resultant structure and then planarized leaving a portion of the polysilicon layer above the active region of the substrate. The remaining portion is doped to form an elevated active region.

摘要翻译： 公开了一种半导体器件及其制造方法，其中通过在半导体衬底的表面上形成栅极/氮化物层结构形成升高的活性多晶硅区域，其中间隔物形成在相邻的壁上以限定衬底的有源区 。 在所得结构上形成厚的多晶硅层，然后平坦化，留下多晶硅层的一部分在衬底的有源区上方。 剩余的部分被掺杂以形成升高的有源区。

公开(公告)号：US5841168A

公开(公告)日：1998-11-24

申请号：US934509

申请日：1997-09-19

申请人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66659 ,  H01L29/7835 ,  H01L29/6656 ,  Y10S257/90

摘要： A method of fabricating a high performance asymmetrical field effect transistor (FET)includes the steps of forming a gate oxide and a gate electrode on a layer of semiconductor material of a first conductivity type. The gate electrode includes a first side edge adjacent a first region of the semiconductor material and a second side edge proximate a second region of the semiconductor material. First and second lightly doped regions are formed in regions of the semiconductor material not covered by the gate oxide, and extending away from the first and second side edges of the gate electrode, respectively. First and second sidewall spacers are formed proximate the first and second side edges of the gate electrode, respectively, each sidewall spacer including a composite sidewall spacer of a first and a second spacer material. Lastly, a very highly doped source region and a highly doped drain region are formed in the first and second regions, respectively, the very highly doped source region having a greater dopant concentration of the second conductivity type than the highly doped drain region and the highly doped drain region having a dopant concentration greater than the lightly doped region extending away from the second side edge of said gate electrode. A novel FET is disclosed also.

摘要翻译： 制造高性能不对称场效应晶体管（FET）的方法包括在第一导电类型的半导体材料层上形成栅极氧化物和栅电极的步骤。 栅电极包括与半导体材料的第一区域相邻的第一侧边缘和靠近半导体材料的第二区域的第二侧边缘。 第一和第二轻掺杂区域形成在半导体材料未被栅极氧化物覆盖的区域中，并且分别从栅电极的第一和第二侧边缘延伸。 第一和第二侧壁间隔物分别形成在栅电极的第一和第二侧边缘附近，每个侧壁间隔物包括第一和第二间隔物材料的复合侧壁间隔物。 最后，分别在第一和第二区域中形成非常高掺杂的源极区和高掺杂的漏极区，非常高掺杂的源极区具有比高掺杂漏极区高的掺杂浓度的第二导电类型， 掺杂浓度的漏极区域的掺杂浓度大于远离所述栅电极的第二侧边缘延伸的轻掺杂区域。 还公开了一种新颖的FET。

公开(公告)号：US5818069A

公开(公告)日：1998-10-06

申请号：US879509

申请日：1997-06-20

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L27/06 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L27/0688

摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

公开(公告)号：US5808319A

公开(公告)日：1998-09-15

申请号：US728601

申请日：1996-10-10

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/76 ,  H01L31/20 ,  H01L31/076

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.

摘要翻译： 一种双级晶体管集成电路和用于制造集成电路的制造技术。 双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管 。 第一局部衬底形成在第一衬底间电介质上。 通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。 集成电路包括半导体全局基板。 集成电路还包括第一晶体管。 第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。 集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。 第一局部衬底形成在第一衬底间电介质的上表面上。 第二晶体管位于第一局部衬底内。 第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

公开(公告)号：US5780340A

公开(公告)日：1998-07-14

申请号：US739566

申请日：1996-10-30

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。

公开(公告)号：US5714394A

公开(公告)日：1998-02-03

申请号：US745029

申请日：1996-11-07

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

摘要翻译： 提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。 因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。 多级制造过程不仅增加了整体电路密度，而且重点放在了在不同级别上的器件之间的高性能互连。 互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。 该互连方案通过在较低级晶体管的栅极导体上形成上级晶体管的栅极导体来降低电阻率。 或者，栅极导体可以是单个导电实体。 为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。 除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。 互连一对堆叠晶体管的栅极导体和连接这些晶体管的特定接头允许开发高密度NAND门。 NAND门包括两对堆叠晶体管，其中一对晶体管可以连接到该对的另一个晶体管或连接到另一对的一个或两个晶体管。

公开(公告)号：US5656518A

公开(公告)日：1997-08-12

申请号：US713386

申请日：1996-09-13

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. The present invention includes a gate insulator and a gate electrode, such as a polysilicon, formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted to provide a lightly doped drain region substantially aligned with the second sidewall. An oxide layer provides first and second sidewall oxide regions adjacent the first and second sidewalls, respectively. The first sidewall oxide region is isolated using a nitride layer having a window which exposes the second sidewall oxide region. Thermal oxidation is applied to the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant. The first sidewall oxide region is then exposed by removing the nitride layer and a second dopant is implanted to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.

摘要翻译： 在本发明中，描述了用于制造非对称LDD-IGFET的方法。 本发明包括形成在半导体衬底上的栅极绝缘体和诸如多晶硅的栅电极，栅电极具有顶表面和相对的第一和第二侧壁。 植入第一掺杂剂以提供基本上与第二侧壁对准的轻掺杂漏极区。 氧化物层分别提供与第一和第二侧壁相邻的第一和第二侧壁氧化物区域。 使用具有暴露第二侧壁氧化物区域的窗口的氮化物层来隔离第一侧壁氧化物区域。 热氧化被施加到第二侧壁氧化物区域，其中第二侧壁氧化物区域的尺寸增加，而第一侧壁氧化物区域的尺寸保持基本恒定。 然后通过去除氮化物层来暴露第一侧壁氧化物区域，并且注入第二掺杂剂以提供与第二侧壁氧化物区域的外边缘基本对准的重掺杂漏极区域和重掺杂源极区域。

公开(公告)号：US07315765B1

公开(公告)日：2008-01-01

申请号：US11192691

申请日：2005-07-29

申请人： Alan Grosvenor Ranft ,  Daniel Kadosh

发明人： Alan Grosvenor Ranft ,  Daniel Kadosh

IPC分类号： G06F19/00

CPC分类号： G05B19/404 ,  G05B19/4187 ,  G05B2219/32297 ,  G05B2219/45031 ,  Y02P90/205

摘要： A method, apparatus, and a system for determining a control thread based upon a process result are provided. At least one post-process parameter is received. The post parameter relates to a first workpiece upon which a plurality of processes have been performed by a plurality of processing tools. A combination of at least a portion of the plurality of processing tools is selected based upon the post-process parameter.

摘要翻译： 提供了一种基于处理结果来确定控制线程的方法，装置和系统。 接收至少一个后处理参数。 后参数涉及由多个处理工具执行多个处理的第一工件。 基于后处理参数来选择多个处理工具的至少一部分的组合。

公开(公告)号：US07248939B1

公开(公告)日：2007-07-24

申请号：US11035276

申请日：2005-01-13

申请人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

发明人： Kevin Andrew Chamness ,  Daniel Kadosh ,  Gregory A. Cherry ,  Jason Williams

IPC分类号： G06F19/00

CPC分类号： H01L21/67288 ,  H01L21/67276

摘要： The present invention provides a method and apparatus for multivariate fault identification and classification. The method includes accessing data indicative of a plurality of physical parameters associated with a plurality of processed semiconductor wafers and providing at least one summary report including information indicative of at least one univariate representation of the accessed data and at least one multivariate representation of the accessed data.

摘要翻译： 本发明提供了一种用于多变量故障识别和分类的方法和装置。 该方法包括访问指示与多个处理的半导体晶片相关联的多个物理参数的数据，并且提供包括指示所访问数据的至少一个单变量表示的信息的至少一个概要报告和所访问数据的至少一个多变量表示 。

公开(公告)号：US06403979B1

公开(公告)日：2002-06-11

申请号：US09780834

申请日：2001-02-09

申请人： Daniel Kadosh ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L2358

CPC分类号： H01L22/34

摘要： A test structure for use in determining an effective channel length of a transistor is disclosed herein. The test structure comprises a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and a plurality of conductive contacts electrically coupled to each of the first and second doped regions. The method disclosed herein comprises determining the extent of lateral encroachment of the doped regions under the structures based upon the following formula: &Dgr;w=(R1W1 −R2W2)/(R1−R2). The effective channel length of the transistor may be determined by subtracting the &Dgr;w value from the length of the gate electrode.

摘要翻译： 本文公开了用于确定晶体管的有效沟道长度的测试结构。 测试结构包括第一电阻器，该第一电阻器由形成在半导体衬底中的第一掺杂区域构成，位于衬底上方的第一对隔开的结构之间，第一电阻器具有由第一对结构之间的间隔限定的第一宽度， 第二电阻器，包括形成在衬底中的位于衬底上方的第二对隔开的结构之间的第二掺杂区域，第二电阻器具有由第二对结构之间的间隔限定的第二宽度，第二宽度更大 并且多个导电触点电耦合到第一和第二掺杂区域中的每一个。 本文公开的方法包括基于以下公式确定结构下的掺杂区域的横向侵入的程度：DELTAw =（R1W1-R2W2）/（R1-R2）。 可以通过从栅电极的长度减去DELTAw值来确定晶体管的有效沟道长度。