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156 条记录 (耗时 0.024 秒)

    COMPUTER MEMORY DEVICE WITH STATUS REGISTER
    81.
    发明申请
    COMPUTER MEMORY DEVICE WITH STATUS REGISTER 有权
    具有状态寄存器的计算机存储器件

    公开(公告)号：US20100095050A1

    公开(公告)日：2010-04-15

    申请号：US12252170

    申请日：2008-10-15

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Hongyue Liu ,  Hai Li

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Hongyue Liu ,  Hai Li

    IPC分类号： G06F12/02

    CPC分类号： G11C7/24 ,  G11C5/143 ,  G11C11/16 ,  G11C13/0002

    摘要： Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.

    摘要翻译： 用于操作具有状态寄存器的存储器件的方法和装置。 在一些实施例中，存储器件具有由至少电阻式感测存储器组成的多个单独可编程的非易失性存储器单元。 在一些实施例中，存储器装置接合接口并维持状态寄存器，在数据传输操作期间至少记录错误或忙信号。

    STATIC SOURCE PLANE IN STRAM
    82.
    发明申请
    STATIC SOURCE PLANE IN STRAM 有权
    静态源平面图

    公开(公告)号：US20100080053A1

    公开(公告)日：2010-04-01

    申请号：US12242331

    申请日：2008-09-30

    申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

    发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

    IPC分类号： G11C11/02 ,  G11C11/409

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.

    摘要翻译： 本公开涉及包括以阵列布置的多个磁性隧道结单元的存储器阵列。 每个磁性隧道结单元电连接在位线和源极线之间。 磁性隧道结单元通过使通过磁性隧道结单元的写入电流通过而在高电阻状态和低电阻状态之间切换。 晶体管电连接在磁性隧道结电池和源极线之间。 字线电耦合到晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。

    MRAM DIODE ARRAY AND ACCESS METHOD
    84.
    发明申请
    MRAM DIODE ARRAY AND ACCESS METHOD 有权
    MRAM二极管阵列和访问方法

    公开(公告)号：US20130003448A1

    公开(公告)日：2013-01-03

    申请号：US13611225

    申请日：2012-09-12

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    MRAM diode array and access method
    85.
    发明授权
    MRAM diode array and access method 有权
    MRAM二极管阵列和访问方式

    公开(公告)号：US08289746B2

    公开(公告)日：2012-10-16

    申请号：US12948824

    申请日：2010-11-18

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C5/08 ,  G11C27/00 ,  G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    Spin-transfer torque memory self-reference read method
    86.
    发明授权
    Spin-transfer torque memory self-reference read method 有权
    自旋转矩存储器自参考读取方式

    公开(公告)号：US08116122B2

    公开(公告)日：2012-02-14

    申请号：US12147723

    申请日：2008-06-27

    申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

    发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006 ,  Y10S977/933

    摘要： A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

    摘要翻译： 描述了自旋转移力矩存储装置和自参考读取方案。 读取自旋传递转矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压，所述磁性隧道结数据单元具有第一电阻状态并存储 第一电压存储装置中的第一位线读取电压。 然后通过磁性隧道结数据单元施加低电阻状态的极化写入电流，形成低的第二电阻状态磁隧道结数据单元。 第二读取电流通过低的第二电阻状态磁隧道结数据单元施加以形成第二位线读取电压。 第二位线读取电压被存储在第二电压存储装置中。 该方法还包括将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

    Variable write and read methods for resistive random access memory
    88.
    发明授权
    Variable write and read methods for resistive random access memory 失效
    电阻随机存取存储器的可变写和读方法

    公开(公告)号：US08054675B2

    公开(公告)日：2011-11-08

    申请号：US13028246

    申请日：2011-02-16

    申请人： Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

    发明人： Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC分类号： G11C11/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057

    摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

    摘要翻译： 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。

    Write method with voltage line tuning
    89.
    发明授权
    Write method with voltage line tuning 有权
    带电压调谐的写入方式

    公开(公告)号：US07944730B2

    公开(公告)日：2011-05-17

    申请号：US12412546

    申请日：2009-03-27

    申请人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

    发明人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

    摘要： A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.

    摘要翻译： 写入电阻式读出存储器单元的方法包括在电阻读出存储单元和半导体晶体管两端施加第一电压以将第一数据状态写入电阻读出存储单元。 第一电压在第一方向通过电阻读出存储单元形成第一持续时间的第一写入电流。 然后，该方法包括在电阻读出存储单元和晶体管两端施加第二电压以将第二数据状态写入电阻读出存储单元。 第二电压在第二方向通过电阻读出存储器单元形成第二持续时间的第二写入电流。 第二方向与第一方向相反，第一电压具有与第二电压不同的值，并且第一持续时间基本上与第二持续时间相同。

    NON VOLATILE MEMORY HAVING INCREASED SENSING MARGIN
    90.
    发明申请
    NON VOLATILE MEMORY HAVING INCREASED SENSING MARGIN 审中-公开
    非挥发性记忆具有增加的感觉尺寸

    公开(公告)号：US20100128519A1

    公开(公告)日：2010-05-27

    申请号：US12500172

    申请日：2009-07-09

    申请人： Hai Li ,  Yiran Chen ,  Xiaobin Wang ,  Yuan Yan

    发明人： Hai Li ,  Yiran Chen ,  Xiaobin Wang ,  Yuan Yan

    IPC分类号： G11C11/14 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C11/1673 ,  G11C11/1659

    摘要： A non volatile memory assembly that includes a reference element having: a reference component; and a reference transistor, wherein the reference component is electrically connected to the reference transistor, and the reference transistor controls the passage of current across the reference component; and at least one non volatile memory element having: a non volatile memory cell, having at least a low and a high resistance state; and an output that electrically connects the reference element with the at least one non volatile memory element, wherein the reference transistor and the memory transistor are activated by a reference gate voltage and a memory gate voltage respectively, and the reference gate voltage and the memory gate voltage are not the same.

    摘要翻译： 一种非易失性存储器组件，其包括具有参考部件的参考元件; 以及参考晶体管，其中所述参考分量电连接到所述参考晶体管，并且所述参考晶体管控制电流通过所述参考分量; 以及至少一个非易失性存储元件，其具有：具有至少低电阻和高电阻状态的非易失性存储单元; 以及输出，其将所述参考元件与所述至少一个非易失性存储元件电连接，其中所述参考晶体管和所述存储晶体管分别由参考栅极电压和存储栅极电压激活，并且所述参考栅极电压和所述存储器栅极 电压不一样。