公开(公告)号：US20090141576A1

公开(公告)日：2009-06-04

申请号：US11949639

申请日：2007-12-03

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

摘要翻译： 一种包括存储位置的集成设备，其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。 第一时间段提供第一预定持续时间。 在第一时间段结束之后，数据以第二预定刷新率反复刷新。

公开(公告)号：US07477717B2

公开(公告)日：2009-01-13

申请号：US10831001

申请日：2004-04-23

申请人： Maksim Kuzmenka ,  Hermann Ruckerbauer

发明人： Maksim Kuzmenka ,  Hermann Ruckerbauer

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

摘要翻译： 提供输入接收器电路，用于接收噪声高速输入信号并产生与高速输入信号的速度相比可以以低采集速度处理的多个输出信号。 输入接收电路包括用于接收高速输入信号（数据）的输入端，多个积分元件和用于将输入连接到多个积分元件中的一个用于积分高速输入信号的开关。 输入接收电路还包括多个用于一次接收集成高速输入信号之一并用于一次输出多个输出信号中的一个的装置，以及用于控制开关的控制器。

公开(公告)号：US20070194447A1

公开(公告)日：2007-08-23

申请号：US11657407

申请日：2007-01-24

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the underside and top side of the chip housing in such a way that a loop back interconnection of a plurality of semiconductor components stacked one on top of another is made possible without subsequent structural alterations to the chip housings thereof.

摘要翻译： 半导体部件包括集成半导体芯片和芯片壳体。 芯片壳体具有将半导体芯片的输入和输出连接连接到芯片壳体的下侧和顶侧上的外部接触连接的第一，第二，第三和第四导体轨迹，使得多个 使其一个堆叠在另一个之上的半导体部件成为可能，而不会对其芯片壳体进行后续的结构改变。

公开(公告)号：US20070194446A1

公开(公告)日：2007-08-23

申请号：US11657387

申请日：2007-01-24

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/14 ,  G11C5/04 ,  H01L2924/15311 ,  H05K1/0295 ,  H05K1/117 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204

摘要： A memory module is proposed which has a first contact bank at a first edge of its electronic printed circuit board and a second contact bank at a second edge. The printed circuit board has first lines that reach from the first contact bank as far as input connections of at least some of the semiconductor components. The printed circuit board has second conductor lines that reach from output connections of at least some of the semiconductor components as far as the first contact bank. The printed circuit board has third conductor lines that reach from output connections of at least some of the semiconductor components as far as the second contact bank. The printed circuit board has fourth conductor lines that reach from the second contact bank as far as input connections of at least some of the semiconductor components.

摘要翻译： 提出一种存储器模块，其在其电子印刷电路板的第一边缘处具有第一触点组，在第二边缘处具有第二触点组。 印刷电路板具有从第一触点组到达至少一些半导体部件的输入连接的第一线。 印刷电路板具有从至少一些半导体部件的输出连接到达第一触点组的第二导体线。 印刷电路板具有从至少一些半导体部件的输出连接到达第二触点组的第三导体线。 印刷电路板具有从第二触点组到达至少一些半导体部件的输入连接的第四导体线。

公开(公告)号：US20070150792A1

公开(公告)日：2007-06-28

申请号：US11559323

申请日：2006-11-13

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C29/00

CPC分类号： G06F11/1012 ,  G11C5/04

摘要： A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group

摘要翻译： 存储器模块以码字的形式存储数据，每个码字包括有用位和用于纠错的校验位。 存储器模块包括第一组存储器件，包括校验位和包括有用位的第二组存储器件，构成等级的第二组存储器件，每个等级作为整体寻址，排列形成等级组，每个等级 组包括至少两个等级和第一组存储设备。 存储器模块还包括一个连接装置，其传送每个包含有用位的位分组，并且以存储器模块的接口和所选择的等级组的存储器件之间的并行格式的校验位

公开(公告)号：US07222271B2

公开(公告)日：2007-05-22

申请号：US10133795

申请日：2002-04-26

申请人： Hermann Ruckerbauer ,  Florian Schamberger

发明人： Hermann Ruckerbauer ,  Florian Schamberger

IPC分类号： G11C29/00

CPC分类号： G11C29/78

摘要： Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorithm. Further, the method can include determining the addresses of faulty memory cells. The method can also include setting a data bit initiating a repair mode in response to detecting a bit error. In the repair mode, a signal present on a data line to the memory chips can be interpreted as a repair command to perform a repair. In addition, the method can include repairing the bit errors by activating redundant memory cells.

摘要翻译： 修复存储芯片硬件故障的方法。 根据一个实施例，提供了一种用于修复具有多个存储器单元的存储器芯片中的位错误的方法。 该方法可以包括使用错误识别算法检测比特错误。 此外，该方法可以包括确定故障存储器单元的地址。 该方法还可以包括响应于检测到位错误而设置启动修复模式的数据位。 在修复模式中，存在于存储器芯片的数据线上的信号可被解释为执行修复的修复命令。 此外，该方法可以包括通过激活冗余存储器单元来修复位错误。

公开(公告)号：US20070025131A1

公开(公告)日：2007-02-01

申请号：US11192335

申请日：2005-07-29

申请人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

发明人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C5/06 ,  H05K1/142

摘要： The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

摘要翻译： 本发明包括半导体存储器模块和使用其的半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

公开(公告)号：US20060265543A1

公开(公告)日：2006-11-23

申请号：US11130412

申请日：2005-05-17

申请人： Peter Oeschay ,  Hermann Ruckerbauer

发明人： Peter Oeschay ,  Hermann Ruckerbauer

IPC分类号： G06F12/06

CPC分类号： G06F12/0676 ,  G11C5/066 ,  G11C8/12

摘要： A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.

摘要翻译： 一种用于设置具有沿着字节通道分配的存储器芯片数量的存储器模块中的等级地址的方法，包括：将字节通道的第一存储器芯片设置为具有第一等级地址，从第一级地址生成第二等级地址 并且将第二等级地址驱动到第二个存储器芯片。 或者，第一等级地址可以被驱动到第二存储器芯片，然后在该第二存储器芯片中产生第二等级地址。 此外，响应于驱动第二/第一等级地址，将第二存储器芯片设置为具有第二等级地址。 通过串行管理总线或命令地址总线发送电源后的上电序列，或命令信号可以用来启动等级的设置。 等级地址沿着字节通道被DQ线重新驱动到相邻的存储器芯片。

公开(公告)号：US20060248260A1

公开(公告)日：2006-11-02

申请号：US11392217

申请日：2006-03-29

申请人： Maksim Kuzmenka ,  Simon Muff ,  Hermann Ruckerbauer

发明人： Maksim Kuzmenka ,  Simon Muff ,  Hermann Ruckerbauer

IPC分类号： G06F12/02

CPC分类号： H03K19/018514 ,  H03K19/0175 ,  H03K19/01812

摘要： A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.

摘要翻译： 电路系统包括用于通过差分控制信号控制第一和第二存储器单元的装置。 差分控制信号包括第一控制信号和第二控制信号，其被反转到第一控制信号。 此外，电路系统包括差分控制信号线，其包括用于路由第一控制信号的第一信号线和用于路由第二控制信号的第二信号线。 第一开关单元经由第一信号线连接，第二电路单元经由第二信号线连接到控制装置。

公开(公告)号：US07061784B2

公开(公告)日：2006-06-13

申请号：US10886814

申请日：2004-07-08

申请人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

发明人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G11C5/063 ,  G11C7/10

摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

摘要翻译： 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。