公开(公告)号：US07515656B2

公开(公告)日：2009-04-07

申请号：US10405370

申请日：2003-04-03

申请人： Hisakatsu Yamaguchi ,  Hirotaka Tamura

发明人： Hisakatsu Yamaguchi ,  Hirotaka Tamura

IPC分类号： H04L27/00

CPC分类号： H03L7/091 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  H04L7/0331

摘要： A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.

摘要翻译： 时钟恢复电路具有根据第一信号检测输入信号中的边界的边界检测电路，并且根据检测到的边界通过控制第一信号的定时来执行时钟的恢复。 时钟恢复电路具有边界检测定时改变电路和变化减小电路。 边界检测定时变化电路通过对第一信号施加变化动态地改变边界检测电路中的边界检测定时，并且变化减小电路根据边界检测定时的动态变化减少在恢复的时钟中发生的相位变化 由边界检测定时变化电路执行。

公开(公告)号：US07389097B2

公开(公告)日：2008-06-17

申请号：US10931201

申请日：2004-09-01

申请人： Hirotaka Tamura

发明人： Hirotaka Tamura

IPC分类号： H04B1/18

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45762 ,  H03F3/45986 ,  H04L5/14 ,  H04L5/1461 ,  H04L7/033 ,  H04L25/0274 ,  H04L25/0292 ,  H04L25/061

摘要： A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

摘要翻译： 接收机具有用于向输入信号施加已知偏移的偏移应用电路，以及用于将偏移施加的输入信号与参考电压进行比较的判定电路。 输入信号的电平根据已知偏移量和决策电路的结果输出来确定。 通过这种配置，可以在用于信号传输的电路中消除大的共模电压。

公开(公告)号：US07173965B2

公开(公告)日：2007-02-06

申请号：US10357691

申请日：2003-02-03

申请人： Yoichi Koyanagi ,  Yasuo Hidaka ,  Weixin Gai ,  Hirotaka Tamura

发明人： Yoichi Koyanagi ,  Yasuo Hidaka ,  Weixin Gai ,  Hirotaka Tamura

IPC分类号： H03K5/159 ,  H04B3/04 ,  H04B3/14 ,  H01P9/00

CPC分类号： H04L25/03343

摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

摘要翻译： 信号均衡包括接收具有振幅的数据序列信号。 确定可操作以均衡数据序列信号的数据序列信号的调整。 产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。 使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。

公开(公告)号：US20060274837A1

公开(公告)日：2006-12-07

申请号：US11505456

申请日：2006-08-17

申请人： Yoshiyasu Doi ,  Satoshi Matsubara ,  Hirotaka Tamura

发明人： Yoshiyasu Doi ,  Satoshi Matsubara ,  Hirotaka Tamura

IPC分类号： H04L25/00 ,  H04L27/00

CPC分类号： H03K5/2481 ,  G11C27/02 ,  H03F2203/7236 ,  H03K5/249

摘要： A receiver circuit has a sampling circuit, a buffer circuit, a determining circuit, and a buffer control circuit. The sampling circuit samples an input signal, and the buffer circuit buffers an output of the sampling circuit. The determining circuit determines an output of the buffer circuit, and the buffer control circuit keeps a small input signal dependency of the output of the buffer circuit until carrying out the sampling. Consequently, an inter symbol interference caused by characteristics of a transmission path which poses a problem for receiving a high-speed signal can be invalidated, and therefore the high-speed received signal can be determined with a higher accuracy.

摘要翻译： 接收器电路具有采样电路，缓冲电路，确定电路和缓冲器控制电路。 采样电路对输入信号进行采样，缓冲电路对采样电路的输出进行缓冲。 确定电路确定缓冲电路的输出，并且缓冲器控制电路保持缓冲电路的输出的小的输入信号依赖性，直到进行采样。 因此，由于传输路径的特性导致的接收高速信号的问题引起的符号间干扰可能无效，因此能够以更高的精度确定高速接收信号。

公开(公告)号：US06963237B2

公开(公告)日：2005-11-08

申请号：US10945965

申请日：2004-09-22

申请人： Hirotaka Tamura ,  Masaya Kibune

发明人： Hirotaka Tamura ,  Masaya Kibune

IPC分类号： H03K5/00 ,  H03F3/45 ,  H03K19/0175 ,  G06F1/04

CPC分类号： H03F3/4565 ,  H03F3/45192 ,  H03F3/45237 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45446

摘要： An output circuit device has an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor. A control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.

摘要翻译： 输出电路装置具有通过具有至少一个隔离晶体管的控制电路连接在第一电源线和第二电源线之间的输出电路。 将保持在恒定电平的控制电压施加到隔离晶体管的控制电极，并且控制电压是可以使包含在从第一或第二电源提供的电压中包含的高频分量衰减的电平的电压 线。

公开(公告)号：US06812777B2

公开(公告)日：2004-11-02

申请号：US10328002

申请日：2002-12-26

申请人： Hirotaka Tamura ,  Masaya Kibune

发明人： Hirotaka Tamura ,  Masaya Kibune

IPC分类号： G05F110

CPC分类号： H03F3/4565 ,  H03F3/45192 ,  H03F3/45237 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45446

摘要： An output circuit device has an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor. A control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.

摘要翻译： 输出电路装置具有通过具有至少一个隔离晶体管的控制电路连接在第一电源线和第二电源线之间的输出电路。 将保持在恒定电平的控制电压施加到隔离晶体管的控制电极，并且控制电压是可以使包含在从第一或第二电源提供的电压中包含的高频分量衰减的电平的电压 线。

公开(公告)号：US06191441B1

公开(公告)日：2001-02-20

申请号：US09178426

申请日：1998-10-26

申请人： Masaki Aoki ,  Hirotaka Tamura ,  Hideki Takauchi ,  Takashi Eshita

发明人： Masaki Aoki ,  Hirotaka Tamura ,  Hideki Takauchi ,  Takashi Eshita

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291

摘要： A ferroelectric memory capable of writing data at a small operation voltage has an insulated-gate field effect transistor, a ferroelectric film, and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the insulated gate. A ferroelectric memory device with a simple structure has an insulated-gate field effect transistor including a source, a drain, and an insulated gate, and a ferroelectric capacitor connected between the drain and the insulated gate.

摘要翻译： 能够以小的操作电压写入数据的铁电存储器具有绝缘栅场效应晶体管，铁电体膜和形成在铁电体膜上并且彼此面对的一对电容器电极，所述一对电容器电极中的一个电气 连接到绝缘门。 具有简单结构的铁电存储器件具有包括源极，漏极和绝缘栅极的绝缘栅场效应晶体管和连接在漏极和绝缘栅极之间的铁电电容器。

公开(公告)号：US5291274A

公开(公告)日：1994-03-01

申请号：US779004

申请日：1991-11-20

申请人： Hirotaka Tamura

发明人： Hirotaka Tamura

IPC分类号： H01L45/00 ,  H01L29/06 ,  H01L39/22

CPC分类号： H01L45/00 ,  Y10S505/702

摘要： An electron device comprises a first dielectric layer (103) having a first thickness determined to allow the tunneling of carriers therethrough and a first dielectric constant, a second dielectric layer (104) provided in contact with the first dielectric layer, the second dielectric layer having a second thickness substantially larger than the first thickness and a second dielectric constant that is substantially larger than the first dielectric constant, a first electrode (101) provided on the first dielectric layer for injecting the carriers, and a second electrode (108) provided in contact with the second dielectric layer for controlling a flow of the carriers through the second dielectric layer in response to a control voltage supplied thereto.

摘要翻译： PCT No.PCT / JP91 / 00372 Sec。 371日期1991年11月20日 102（e）1991年11月20日日期PCT 1991年3月20日PCT PCT。 出版物WO91 / 15033 日期：1991年10月3日。电子器件包括第一介电层（103），其具有确定允许载流子穿透其中的第一厚度和第一介电常数的第一介电层（103），与第一介电层 层，所述第二介电层具有基本上大于所述第一厚度的第二厚度和基本上大于所述第一介电常数的第二介电常数;设置在所述第一介电层上用于注入载流子的第一电极， 第二电极（108），其设置成与第二电介质层接触，用于响应于提供给其的控制电压来控制载流子通过第二介电层的流动。