公开(公告)号：US06191441B1

公开(公告)日：2001-02-20

申请号：US09178426

申请日：1998-10-26

申请人： Masaki Aoki ,  Hirotaka Tamura ,  Hideki Takauchi ,  Takashi Eshita

发明人： Masaki Aoki ,  Hirotaka Tamura ,  Hideki Takauchi ,  Takashi Eshita

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291

摘要： A ferroelectric memory capable of writing data at a small operation voltage has an insulated-gate field effect transistor, a ferroelectric film, and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the insulated gate. A ferroelectric memory device with a simple structure has an insulated-gate field effect transistor including a source, a drain, and an insulated gate, and a ferroelectric capacitor connected between the drain and the insulated gate.

摘要翻译： 能够以小的操作电压写入数据的铁电存储器具有绝缘栅场效应晶体管，铁电体膜和形成在铁电体膜上并且彼此面对的一对电容器电极，所述一对电容器电极中的一个电气 连接到绝缘门。 具有简单结构的铁电存储器件具有包括源极，漏极和绝缘栅极的绝缘栅场效应晶体管和连接在漏极和绝缘栅极之间的铁电电容器。

公开(公告)号：US6046929A

公开(公告)日：2000-04-04

申请号：US282469

申请日：1999-03-31

申请人： Masaki Aoki ,  Akio Itoh ,  Mitsuteru Mushiga ,  Ko Nakamura ,  Takashi Eshita

发明人： Masaki Aoki ,  Akio Itoh ,  Mitsuteru Mushiga ,  Ko Nakamura ,  Takashi Eshita

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507 ,  G11C11/223

摘要： The source region and gate electrode of a field effect transistor including a drain region and a gate electrode in addition to the source region are connected by a first ferroelectric capacitor. The drain region and gate electrode are connected by a second ferroelectric capacitor. A ferroelectric memory device suitable for high integration is provided.

摘要翻译： 除了源极区域之外，包括漏极区域和栅极电极的源极区域和栅极电极通过第一铁电体电容器连接。 漏区和栅极通过第二铁电电容器连接。 提供了适用于高集成度的铁电存储器件。

公开(公告)号：US5518937A

公开(公告)日：1996-05-21

申请号：US407254

申请日：1995-03-20

申请人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

发明人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

IPC分类号： H01L29/08 ,  H01L29/16 ,  H01L29/36 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/0817 ,  H01L29/1604 ,  H01L29/36 ,  H01L29/7375

摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.

摘要翻译： 双极晶体管包括由掺杂有第一杂质的硅晶体制成的第一电平的基极区域，以便在基极区域中建立第一载流子浓度，并且将由掺杂有第二杂质的硅晶体制成的发射极区域基本上 大于第一电平预定因子，以便在第二杂质超过硅晶体中的第二杂质的溶解度极限的发射极区域中建立第二载流子浓度。 第一和第二电平在这样一个范围内选择，使得发射极区域和基极区域之间的载流子浓度的差异随着基极区域中的杂质水平的增加而显着降低。

公开(公告)号：US5111266A

公开(公告)日：1992-05-05

申请号：US714367

申请日：1991-06-12

申请人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

发明人： Yuji Furumura ,  Fumitake Mieno ,  Tsutomu Nakazawa ,  Takashi Eshita ,  Mamoru Maeda ,  Tsunenori Yamauchi

IPC分类号： H01L29/08 ,  H01L29/16 ,  H01L29/36 ,  H01L29/737

CPC分类号： H01L29/0817 ,  H01L29/1604 ,  H01L29/36 ,  H01L29/7375

摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.

公开(公告)号：US5834362A

公开(公告)日：1998-11-10

申请号：US619249

申请日：1996-03-21

申请人： Shinji Miyagaki ,  Takashi Eshita ,  Satoshi Ohkubo ,  Kazuaki Takai

发明人： Shinji Miyagaki ,  Takashi Eshita ,  Satoshi Ohkubo ,  Kazuaki Takai

IPC分类号： H01L21/20 ,  H01L21/335 ,  H01L21/338 ,  H01L21/331 ,  H01L21/36

CPC分类号： H01L21/02461 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02494 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L29/66462

摘要： A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.

摘要翻译： 一种制造化合物半导体器件的方法包括以下步骤：在Si衬底的表面上沉积第一III-V族化合物半导体层，同时将Si衬底的温度保持在第一温度，沉积第二组III-V族化合物 半导体层，同时保持基板的温度处于第二较高温度，并且在第二组III-V族化合物半导体层上沉积第三组III-V族化合物半导体层，同时保持第 在比所述第二温度高的第三温度下的衬底的温度，其中第二组III-V族化合物半导体层含有Al。

公开(公告)号：US5402748A

公开(公告)日：1995-04-04

申请号：US44029

申请日：1993-04-08

申请人： Kazuaki Takai ,  Takashi Eshita

发明人： Kazuaki Takai ,  Takashi Eshita

IPC分类号： C30B25/02 ,  H01L21/205

CPC分类号： C30B25/02 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02661

摘要： A method of fabricating a semiconductor device comprises the steps of growing a first layer of a group III-V compound semiconductor material on a substrate by a vapor phase deposition process by setting the temperature at a first temperature, raising the temperature from the first temperature to a second, higher temperature, growing a second layer of a group III-V compound semiconductor material on the first layer, wherein the step of raising the temperature is conducted while supplying a source gas for the group V element under a condition, determined in terms of a total pressure and a partial pressure of the source gas, such that the condition falls within a region defined by a first condition wherein the total pressure is set to 76 Torr and the partial pressure is set to 0.35 Torr, a second condition wherein the total pressure is set to 760 Torr and the partial pressure is set to 0.6 Torr, a third condition wherein the total pressure is set to 760 Torr and the partial pressure is set to 5.7 Torr, and a fourth condition wherein the total pressure is set to 76 Torr and the partial pressure is set to 1.3 Torr.

摘要翻译： 制造半导体器件的方法包括以下步骤：通过将温度设定在第一温度，通过气相沉积工艺在衬底上生长第III-V族化合物半导体材料的第一层，将温度从第一温度升高到 第二高温，在第一层上生长III-V族化合物半导体材料的第二层，其中提供温度的步骤是在对V族元素提供源气体的条件下进行的， 的总压力和源气体的分压，使得该条件落在由总压力设定为76乇并且分压设定为0.35乇的第一条件限定的区域内，其中第二条件 总压设定为760乇，分压设定为0.6乇，第三条件为总压为760乇，分压为 t至5.7乇，第四条件为总压为76乇，分压设定为1.3乇。

公开(公告)号：US5082695A

公开(公告)日：1992-01-21

申请号：US314794

申请日：1989-02-24

申请人： Masao Yamada ,  Masafumi Nakaishi ,  Kenji Nakagawa ,  Yuji Furumura ,  Takashi Eshita ,  Fumitake Mieno

发明人： Masao Yamada ,  Masafumi Nakaishi ,  Kenji Nakagawa ,  Yuji Furumura ,  Takashi Eshita ,  Fumitake Mieno

IPC分类号： G03F1/22

CPC分类号： G03F1/22

摘要： A method of fabricating an X-ray exposure mask including the steps of forming a .beta.-SiC membrane by chemcial vapor deposition and simultaneously doping the membrane with at least one of phosphorous, boron, nitrogen and oxygen.

公开(公告)号：US06188090B1

公开(公告)日：2001-02-13

申请号：US09026915

申请日：1998-02-20

申请人： Shinji Miyagaki ,  Takashi Eshita ,  Satoshi Ohkubo ,  Kazuaki Takai

发明人： Shinji Miyagaki ,  Takashi Eshita ,  Satoshi Ohkubo ,  Kazuaki Takai

IPC分类号： H01L310328

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02494 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L29/66462

摘要： A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.

摘要翻译： 一种制造化合物半导体器件的方法包括以下步骤：在Si衬底的表面上沉积第一III-V族化合物半导体层，同时将Si衬底的温度保持在第一温度，沉积第二组III-V族化合物 半导体层，同时保持基板的温度处于第二较高温度，并且在第二组III-V族化合物半导体层上沉积第三组III-V族化合物半导体层，同时保持第 在比所述第二温度高的第三温度下的衬底的温度，其中第二组III-V族化合物半导体层含有Al。

公开(公告)号：US5103285A

公开(公告)日：1992-04-07

申请号：US286611

申请日：1988-12-19

申请人： Yuji Furumura ,  Fumitake Mieno ,  Takashi Eshita ,  Kikuo Itoh ,  Masahiko Doki

发明人： Yuji Furumura ,  Fumitake Mieno ,  Takashi Eshita ,  Kikuo Itoh ,  Masahiko Doki

IPC分类号： H01L21/205 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/456

摘要： A silicon carbide layer between a silicon substrate or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD, which has an advantage of a good coverage over a step portion such as a contact window.

公开(公告)号：US5057880A

公开(公告)日：1991-10-15

申请号：US601427

申请日：1990-10-23

申请人： Takashi Eshita ,  Toshikazu Inoue ,  Kanetake Takasaki

发明人： Takashi Eshita ,  Toshikazu Inoue ,  Kanetake Takasaki

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/10

CPC分类号： H01L29/1075 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02546 ,  Y10S257/928

摘要： A semiconductor device comprises a substrate, a compound semiconductor layer provided on the substrate, and an active region formed on the compound semiconductor layer. The substrate in turn comprises a first semiconductor layer of a first semiconductor material, a second semiconductor layer of a second semiconductor material and provided on the first semiconductor layer, and a third semiconductor layer provided on the second semiconductor layer. The third semiconductor layer has a plurality of segments each defined by a pair of side walls that extend substantially perpendicular to the third semiconductor layer. The plurality of segments have a plurality of first-type segments and a plurality of second-type segments wherein the first- and second-type segments are arranged alternately when viewed in a direction parallel to the third semiconductor layer. The first- and second-type segments have respective lattice constants that differ with each other such that a stress field acting substantially perpendicular to the third semiconductor layer is induced in the third semiconductor layer.