公开(公告)号：US09379712B2

公开(公告)日：2016-06-28

申请号：US14813934

申请日：2015-07-30

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K19/16 ,  H03K17/80

CPC classification number: H03K19/16 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3268 ,  H03K17/80

Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

公开(公告)号：US09374162B2

公开(公告)日：2016-06-21

申请号：US13719884

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Johanna M. Swan ,  Dmitri E. Nikonov ,  Raseong Kim

IPC: G02B6/42 ,  H04B10/25 ,  G02B6/43 ,  H04B10/80

CPC classification number: H04B10/2504 ,  G02B6/43 ,  H04B10/801

Abstract: Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described.

Abstract translation: 这里描述了与安装在用于数据通信的便携式设备中的半导体封装有关的技术。 更具体地，描述了在单个模块或模具中包含存储器，数字逻辑芯片和光学端口的半导体封装。

公开(公告)号：US09305629B2

公开(公告)日：2016-04-05

申请号：US13976053

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/14 ,  G11C11/16

Abstract: An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.

Abstract translation: 实施例使用集成到与非CMOS器件相同的芯片上的分布式电容器向超低压非CMOS器件提供功率（具有低电压，高电流和高电流密度）。 例如，实施例提供了一个自旋逻辑门，邻近电介质材料和电容器的第一和第二平板。 电容器使用降压开关模式电源将低电压/高电流放电到自旋逻辑门，该降压开关模式电源在一个时钟周期（使用以第一方向配置的开关元件）充电多个电容器，并在相对时钟内从电容器放电 循环（使用以第二方向配置的开关元件）。 电容器将电流从平面外转移到自旋逻辑器件，而不必横穿长的功率耗散互连路径。 本文描述了其它实施例。

公开(公告)号：US08963135B2

公开(公告)日：2015-02-24

申请号：US13690407

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Robert L. Sankman ,  Raseong Kim ,  Jin Pan

IPC: H01L29/08 ,  G06F19/00 ,  H05K3/46 ,  H05K1/00 ,  H01L51/00 ,  H01L27/06 ,  H01L27/28

CPC classification number: H05K3/4644 ,  B29C64/00 ,  B32B27/06 ,  B32B2457/00 ,  B33Y50/02 ,  B33Y70/00 ,  B33Y80/00 ,  H01L27/0688 ,  H01L27/281 ,  H01L51/0004 ,  H05K1/00

Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.

Abstract translation: 描述了包括半导体有机材料在内的三维集成电路。 在一些实施例中，三维集成电路包括一个或多个电子部件，其包括由一个或多个半导体有机材料形成的半导体区域。 三维集成电路的电子部件还可以包括由有机绝缘材料形成的绝缘区域，并且由导电材料形成导电区域。 三维集成电路可以通过诸如三维印刷之类的添加剂制造工艺形成。 还描述了用于生产和测试三维集成电路的装置和方法。