公开(公告)号：US20160314188A1

公开(公告)日：2016-10-27

申请号：US15198881

申请日：2016-06-30

申请人： Intel Corporation

发明人： Michael P. Mesnier ,  Tian Luo ,  Feng Chen

IPC分类号： G06F17/30 ,  H04L29/08

CPC分类号： G06F16/285 ,  G06F16/22 ,  H04L67/1097 ,  H04L67/322

摘要： In accordance with some embodiments, classification of input/output requests from a database to a storage system may be performed. Each input/output request may be associated with a database class, and each database class may be mapped to a quality of service policy. Thus, quality of service may be enforced such that different data blocks within the storage system of the database may be afforded appropriate quality of service.

摘要翻译： 根据一些实施例，可以执行从数据库到存储系统的输入/输出请求的分类。 每个输入/输出请求可以与数据库类相关联，并且每个数据库类可被映射到服务质量策略。 因此，可以执行服务质量，使得数据库的存储系统内的不同数据块可以被提供适当的服务质量。

公开(公告)号：US12112397B2

公开(公告)日：2024-10-08

申请号：US18334733

申请日：2023-06-14

申请人： Intel Corporation

发明人： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC分类号： G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

CPC分类号： G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

摘要： One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

公开(公告)号：US20240127408A1

公开(公告)日：2024-04-18

申请号：US18514252

申请日：2023-11-20

申请人： Intel Corporation

发明人： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Xiaoming Chen ,  Junjie Huang ,  Tao Lv ,  Yuanke Luo ,  Yi Yang ,  Feng Chen ,  Zhiming Wang ,  Zhiqiao Zheng ,  Shandong Wang

IPC分类号： G06T5/00 ,  G06N3/04

CPC分类号： G06T5/002 ,  G06N3/04 ,  G06T2207/20081 ,  G06T2207/20084

摘要： Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

公开(公告)号：US11727527B2

公开(公告)日：2023-08-15

申请号：US17541413

申请日：2021-12-03

申请人： Intel Corporation

发明人： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC分类号： G06T1/20 ,  G06N3/063 ,  G06F9/38 ,  G06F9/30 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/04 ,  G06N3/08

CPC分类号： G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

公开(公告)号：US11593910B2

公开(公告)日：2023-02-28

申请号：US17741934

申请日：2022-05-11

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06N3/063 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/084 ,  G06F8/41

摘要： Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US20230027203A1

公开(公告)日：2023-01-26

申请号：US17826674

申请日：2022-05-27

申请人： Intel Corporation

发明人： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC分类号： G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11562461B2

公开(公告)日：2023-01-24

申请号：US17529862

申请日：2021-11-18

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06T15/80 ,  G06F3/14 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

公开(公告)号：US20230017304A1

公开(公告)日：2023-01-19

申请号：US17874876

申请日：2022-07-27

申请人： Intel Corporation

发明人： Rajkishore Barik ,  Brian T. Lewis ,  Murali Sundaresan ,  Jeffrey Jackson ,  Feng Chen ,  Xiaoming Chen ,  Mike Macpherson

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N5/00 ,  G06F9/46

摘要： A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

公开(公告)号：US11550600B2

公开(公告)日：2023-01-10

申请号：US17090295

申请日：2020-11-05

申请人： Intel Corporation

发明人： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

IPC分类号： G06F9/448 ,  G06F16/215 ,  G06T1/60 ,  G06T1/20

摘要： Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

公开(公告)号：US11488005B2

公开(公告)日：2022-11-01

申请号：US16518828

申请日：2019-07-22

申请人： Intel Corporation

发明人： Brian T. Lewis ,  Feng Chen ,  Jeffrey R. Jackson ,  Justin E. Gottschlich ,  Rajkishore Barik ,  Xiaoming Chen ,  Prasoonkumar Surti ,  Mike B. Macpherson ,  Murali Sundaresan

IPC分类号： G01C22/00 ,  G06N3/063 ,  B60W30/095 ,  G06N3/00 ,  G06N3/04 ,  G01C21/34

摘要： A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.