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公开(公告)号：US20180260682A1
公开(公告)日：2018-09-13
申请号：US15457658
申请日：2017-03-13
IPC分类号： G06N3/04
CPC分类号： G06N3/0454 , G06N3/049 , G06N3/063
摘要： Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.
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公开(公告)号：US20180253833A1
公开(公告)日：2018-09-06
申请号：US15967373
申请日：2018-04-30
CPC分类号： G06T3/4046 , G06F17/11 , G06K9/4604 , G06K9/66 , G06N3/063 , G06T1/20 , G06T5/006 , G06T2207/20084 , G06T2207/20172
摘要： One or more embodiments provide method for image distortion correction including receiving, by multiple neurosynaptic core circuits, a set of inputs comprising image dimensions and pixel distortion coefficients for at least one image frame via at least one input core circuit. Each distorted pixel is mapped to zero or more undistorted pixels by processing the set of inputs corresponding to each pixel of the at least one image frame by the at least one input core circuit. Corresponding pixel intensity values of each distorted pixel are routed to output undistorted pixels for each image frame via the at least one output core circuit.
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公开(公告)号：US20180253825A1
公开(公告)日：2018-09-06
申请号：US15967362
申请日：2018-04-30
CPC分类号： G06T5/006 , G06F17/11 , G06K9/4604 , G06K9/66 , G06N3/063 , G06T1/20 , G06T3/4046 , G06T2207/20084 , G06T2207/20172
摘要： One or more embodiments provide a neurosynaptic circuit that includes multiple neurosynaptic core circuits that: perform image distortion correction by converting a source image to a destination image by: taking as input a sequence of image frames of a video with one or more channels per frame, and converting dimensions and pixel distortion coefficients of each frame as one or more corresponding neuronal firing events. Each distorted pixel is mapped to zero or more undistorted pixels by processing each neuronal firing event corresponding to each pixel of each image frame. Corresponding pixel intensity values of each distorted pixel are processed to output undistorted pixels for each image frame as neuronal firing events for a spike representation of the destination image.
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84.发明申请公开(公告)号：US20180197074A1
公开(公告)日：2018-07-12
申请号：US15917414
申请日：2018-03-09
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
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85.发明申请公开(公告)号：US20180197073A1
公开(公告)日：2018-07-12
申请号：US15917403
申请日：2018-03-09
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
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公开(公告)号：US10019667B2
公开(公告)日：2018-07-10
申请号：US15184892
申请日：2016-06-16
IPC分类号： G06N3/04
摘要： Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.
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87.发明申请公开(公告)号：US20180189637A1
公开(公告)日：2018-07-05
申请号：US15908415
申请日：2018-02-28
发明人： Arnon Amir , Rathinakumar Appuswamy , Pallab Datta , Myron D. Flickner , Paul A. Merolla , Dharmendra S. Modha , Benjamin G. Shaw
摘要： One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.
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公开(公告)号：US09992057B2
公开(公告)日：2018-06-05
申请号：US14262592
申请日：2014-04-25
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
CPC分类号： H04L41/0668 , G06F11/00 , G06F11/0724 , G06F11/0793 , G06N3/049 , G06N3/063 , H04L41/0659
摘要： Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.
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公开(公告)号：US09984323B2
公开(公告)日：2018-05-29
申请号：US14669575
申请日：2015-03-26
摘要： Embodiments of the invention provide a method comprising maintaining a library of one or more compositional prototypes. Each compositional prototype is associated with a neurosynaptic program. The method further comprises searching the library based on one or more search parameters. At least one compositional prototype satisfying the search parameters is selected. A neurosynaptic network is generated or extended by applying one or more rules associated with the selected compositional prototypes.
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公开(公告)号：US09953261B2
公开(公告)日：2018-04-24
申请号：US14990720
申请日：2016-01-07
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
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