公开(公告)号：US20230197522A1

公开(公告)日：2023-06-22

申请号：US18065130

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack. The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

公开(公告)号：US11682591B2

公开(公告)日：2023-06-20

申请号：US17409964

申请日：2021-08-24

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Juergen Boemmels ,  Basoene Briggs

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/775 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/775 ,  H01L21/823878

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:



forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
the method further comprising, prior to said processing:
by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
depositing a bottom insulating material in said cavities;

wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

公开(公告)号：US11545401B2

公开(公告)日：2023-01-03

申请号：US17114826

申请日：2020-12-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Eugenio Dentoni Litta ,  Liping Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

公开(公告)号：US11430876B2

公开(公告)日：2022-08-30

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US20220068725A1

公开(公告)日：2022-03-03

申请号：US17409964

申请日：2021-08-24

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Juergen Boemmels ,  Basoene Briggs

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:
forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
the method further comprising, prior to said processing:
by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
depositing a bottom insulating material in said cavities;
wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

公开(公告)号：US20210296500A1

公开(公告)日：2021-09-23

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

公开(公告)号：US20210118747A1

公开(公告)日：2021-04-22

申请号：US17074047

申请日：2020-10-19

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Boon Teik Chan ,  Steven Demuynck

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

公开(公告)号：US20210066116A1

公开(公告)日：2021-03-04

申请号：US17006642

申请日：2020-08-28

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

公开(公告)号：US20210035860A1

公开(公告)日：2021-02-04

申请号：US16945858

申请日：2020-08-01

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/8234

Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

公开(公告)号：US20200328122A1

公开(公告)日：2020-10-15

申请号：US16843706

申请日：2020-04-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.