公开(公告)号：US11545401B2

公开(公告)日：2023-01-03

申请号：US17114826

申请日：2020-12-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Eugenio Dentoni Litta ,  Liping Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

公开(公告)号：US20170301583A1

公开(公告)日：2017-10-19

申请号：US15489584

申请日：2017-04-17

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Liping Zhang ,  Mikhail Baklanov

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885

Abstract: A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.

公开(公告)号：US09595422B2

公开(公告)日：2017-03-14

申请号：US15072141

申请日：2016-03-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Mikhaïl Baklanov ,  Liping Zhang ,  Jean-Francois de Marneffe

IPC: B31D3/00 ,  H01J37/32 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01J37/32009 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76826

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to plasma etching of dielectric materials having pores. In one aspect, a method for etching a porous material in an environment includes contacting the porous material with an organic gas at a pressure and a temperature. The organic gas is such that at the pressure and the temperature, the organic gas remains in a gas state when outside of the porous material, while the organic gas condenses into an organic liquid upon contacting the porous material. Upon contacting the porous material, the organic gas thereby fills the pores of the porous material with the organic liquid. Subsequent to contacting the porous material, the method additionally includes plasma etch-treating of the porous material having filled pores, thereby evaporating a fraction of the organic liquid filling the pores of the porous material.

Abstract translation: 所公开的技术通常涉及半导体制造，更具体地涉及具有孔的电介质材料的等离子体蚀刻。 一方面，在环境中蚀刻多孔材料的方法包括在压力和温度下使多孔材料与有机气体接触。 有机气体使得在压力和温度下，有机气体在多孔材料外部保持为气态，而有机气体在与多孔材料接触时冷凝成有机液体。 当接触多孔材料时，有机气体由此用有机液体填充多孔材料的孔隙。 在多孔材料接触之后，该方法另外包括等离子体蚀刻处理具有填充孔的多孔材料，由此蒸发填充多孔材料的孔的有机液体的一部分。

公开(公告)号：US20210175130A1

公开(公告)日：2021-06-10

申请号：US17114826

申请日：2020-12-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Eugenio Dentoni Litta ,  Liping Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

公开(公告)号：US09941151B2

公开(公告)日：2018-04-10

申请号：US15489584

申请日：2017-04-17

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Liping Zhang ,  Mikhail Baklanov

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885

Abstract: A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.

公开(公告)号：US20160276133A1

公开(公告)日：2016-09-22

申请号：US15072141

申请日：2016-03-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Mikhaïl Baklanov ,  Liping Zhang ,  Jean-Francois de Marneffe

IPC: H01J37/32

CPC classification number: H01J37/32009 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76826

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to plasma etching of dielectric materials having pores. In one aspect, a method for etching a porous material in an environment includes contacting the porous material with an organic gas at a pressure and a temperature. The organic gas is such that at the pressure and the temperature, the organic gas remains in a gas state when outside of the porous material, while the organic gas condenses into an organic liquid upon contacting the porous material. Upon contacting the porous material, the organic gas thereby fills the pores of the porous material with the organic liquid. Subsequent to contacting the porous material, the method additionally includes plasma etch-treating of the porous material having filled pores, thereby evaporating a fraction of the organic liquid filling the pores of the porous material.

Abstract translation: 所公开的技术通常涉及半导体制造，更具体地涉及具有孔的电介质材料的等离子体蚀刻。 一方面，在环境中蚀刻多孔材料的方法包括在压力和温度下使多孔材料与有机气体接触。 有机气体使得在压力和温度下，有机气体在多孔材料外部保持为气态，而有机气体在与多孔材料接触时冷凝成有机液体。 当接触多孔材料时，有机气体由此用有机液体填充多孔材料的孔隙。 在多孔材料接触之后，该方法另外包括等离子体蚀刻处理具有填充孔的多孔材料，由此蒸发填充多孔材料的孔的有机液体的一部分。