公开(公告)号：US20200381525A1

公开(公告)日：2020-12-03

申请号：US16999508

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20200303509A1

公开(公告)日：2020-09-24

申请号：US16362510

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.

公开(公告)号：US20190172950A1

公开(公告)日：2019-06-06

申请号：US16323661

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Sean T. MA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Stephen M. CEA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.

公开(公告)号：US20180315838A1

公开(公告)日：2018-11-01

申请号：US15770463

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L29/66439 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20180248005A1

公开(公告)日：2018-08-30

申请号：US15774952

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

公开(公告)号：US20180204955A1

公开(公告)日：2018-07-19

申请号：US15743575

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Szuya S. LIAO ,  Stephen M. CEA

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/775

Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.