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108 条记录 (耗时 0.026 秒)

    Neural network weight distribution from a grid of memory elements
    81.
    发明授权
    Neural network weight distribution from a grid of memory elements 有权

    公开(公告)号：US11521085B2

    公开(公告)日：2022-12-06

    申请号：US16842035

    申请日：2020-04-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Jun Sawada ,  Dharmendra S. Modha ,  Andrew S. Cassidy ,  John V. Arthur ,  Tapan K. Nayak ,  Carlos O. Otero ,  Brian Taba ,  Filipp A. Akopyan ,  Pallab Datta

    IPC分类号： G06N5/04 ,  G06N3/063 ,  G06F17/15 ,  G06F17/16

    摘要： Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

    Fault-tolerant power-driven synthesis
    83.
    发明授权
    Fault-tolerant power-driven synthesis 有权

    公开(公告)号：US11301757B2

    公开(公告)日：2022-04-12

    申请号：US16696968

    申请日：2019-11-26

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhou Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC分类号： G06N3/10

    摘要： Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

    Selective multicast delivery on a bus-based interconnect
    89.
    发明授权
    Selective multicast delivery on a bus-based interconnect 有权

    公开(公告)号：US10834024B2

    公开(公告)日：2020-11-10

    申请号：US16147198

    申请日：2018-09-28

    申请人： International Business Machines Corporation

    发明人： Simon J. Hollis ,  Hartmut Penner ,  Andrew S. Cassidy ,  Jun Sawada ,  Pallab Datta

    IPC分类号： G06F15/16 ,  H04L12/931 ,  G06N3/02 ,  H04L12/18

    摘要： According to one embodiment, a computer program product for performing selective multicast delivery includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, and where the program instructions are executable by a selector of an intelligent processing unit (IPU) to cause the selector to perform a method comprising identifying, by the selector, an address header appended to an instance of data, comparing, by the selector, address data in the address header to identifier data stored at the selector, and conditionally delivering, by the selector, the instance of data, based on the comparing.