公开(公告)号：US20080123426A1

公开(公告)日：2008-05-29

申请号：US11555856

申请日：2006-11-02

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US20080123425A1

公开(公告)日：2008-05-29

申请号：US11555850

申请日：2006-11-02

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/00 ,  G11C16/04

CPC分类号： G11C16/3418

摘要： A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种用于操作减少程序干扰的非易失性存储系统的方法。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US20080074920A1

公开(公告)日：2008-03-27

申请号：US11534139

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US07154779B2

公开(公告)日：2006-12-26

申请号：US10762181

申请日：2004-01-21

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 非易失性存储器件通过经由第二介质区域在浮动栅极和控制栅极之间传送电荷而被编程和/或擦除。

公开(公告)号：US08369149B2

公开(公告)日：2013-02-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US08310870B2

公开(公告)日：2012-11-13

申请号：US12849510

申请日：2010-08-03

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.

摘要翻译： 在非易失性存储器系统中，基于速度的编程速度减慢测量例如升高的位线被应用于更快编程的存储元件。 执行使用来回字线顺序的多相编程操作，其中编程速度数据被存储在一个编程阶段的锁存器中，并且从锁存器读取以用于给定字线的后续编程阶段。 可以通过检测多个存储元件何时达到指定的验证电平，计数基于存储元件的自然阈值电压分布而设置的附加数量的编程脉冲，并且随后执行 一种分离更快和慢速编程存储元件的读取操作。 可以在不同的编程阶段调整漏极侧选择栅极电压，以适应不同的位线偏置电平。

公开(公告)号：US20120163083A1

公开(公告)日：2012-06-28

申请号：US12976893

申请日：2010-12-22

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/24 ,  G11C16/3418 ,  G11C16/3436

摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.

摘要翻译： 在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。 诸如升高的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。 升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。 施加减速措施的编程脉冲的范围可以自适应地固定或确定。 当位线电压降低时，程序脉冲增量可以下降，然后增加。 被编程为最高目标数据状态的存储元件可以从减速测量中排除。

公开(公告)号：US08169822B2

公开(公告)日：2012-05-01

申请号：US12616269

申请日：2009-11-11

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Grishma Shah

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Grishma Shah

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

摘要翻译： 在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。 为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。 可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。 一个共同的升压方案可以用于多个数据状态的组。 可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。 在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

公开(公告)号：US08051240B2

公开(公告)日：2011-11-01

申请号：US12118446

申请日：2008-05-09

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G06F12/00

CPC分类号： G11C16/0483 ,  B05B11/3098 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C2211/5621

摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.

摘要翻译： 获得优化的验证和读取通过电压，以提高非易失性存储设备的读取精度。 当存储元件变为编程时，优化的电压表示未选择的存储元件电阻的变化。 这种电阻变化被称为前模式效应。 在一种方法中，验证通过电压高于读取通过电压，并且在所选字线的源极和漏极侧施加公共验证电压。 在其他方法中，不同的验证通过电压施加在所选字线的源极和漏极侧。 优化过程可以包括确定不同组的验证和读取通过电压的度量。 该度量可以指示ECC解码引擎的阈值电压宽度，读取错误或解码时间或迭代次数。

公开(公告)号：US20110111583A1

公开(公告)日：2011-05-12

申请号：US13010563

申请日：2011-01-20

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。