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    PMOS transistor strain optimization with raised junction regions
    82.
    发明申请
    PMOS transistor strain optimization with raised junction regions 审中-公开
    具有凸起结区域的PMOS晶体管应变优化

    公开(公告)号：US20070034945A1

    公开(公告)日：2007-02-15

    申请号：US11586154

    申请日：2006-10-24

    申请人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    发明人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

    摘要： Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

    摘要翻译： PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。

    Enhancing strained device performance by use of multi narrow section layout
    85.
    发明申请
    Enhancing strained device performance by use of multi narrow section layout 有权
    通过使用多窄截面布局来增强设备的应变性能

    公开(公告)号：US20050221566A1

    公开(公告)日：2005-10-06

    申请号：US10815911

    申请日：2004-03-31

    申请人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    发明人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/80 ,  H01L21/336 ,  H01L31/112

    CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

    摘要： A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

    摘要翻译： 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。