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    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    2.
    发明申请
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 失效
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US20050014351A1

    公开(公告)日：2005-01-20

    申请号：US10918818

    申请日：2004-08-12

    申请人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    发明人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7842

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Field effect transistor structure with abrupt source/drain junctions
    5.
    发明授权
    Field effect transistor structure with abrupt source/drain junctions 有权
    具有突发的源极/漏极结的场效应晶体管结构

    公开(公告)号：US07682916B2

    公开(公告)日：2010-03-23

    申请号：US12231172

    申请日：2008-08-28

    申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    Method of fabricating a field effect transistor structure with abrupt source/drain junctions
    6.
    发明申请
    Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
    制造具有突然的源极/漏极结的场效应晶体管结构的方法

    公开(公告)号：US20060220153A1

    公开(公告)日：2006-10-05

    申请号：US11437569

    申请日：2006-05-19

    申请人： Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    发明人： Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    Method of fabricating a field effect transistor structure with abrupt source/drain junctions
    7.
    发明授权
    Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
    制造具有突然的源极/漏极结的场效应晶体管结构的方法

    公开(公告)号：US07436035B2

    公开(公告)日：2008-10-14

    申请号：US10917722

    申请日：2004-08-12

    申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC分类号： H01L29/72

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    Transistor with minimal junction capacitance and method of fabrication
    8.
    发明授权
    Transistor with minimal junction capacitance and method of fabrication 失效
    具有最小结电容的晶体管和制造方法

    公开(公告)号：US06198142B1

    公开(公告)日：2001-03-06

    申请号：US09127349

    申请日：1998-07-31

    申请人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

    发明人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

    IPC分类号： H01L2976

    CPC分类号： H01L29/66636 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/7834

    摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

    摘要翻译： 在该制造方法中具有最小结电容的新型MOS晶体管。 根据本发明，在半导体衬底的第一表面上形成栅介质层。 然后在栅极电介质层上形成栅电极。 接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。 然后在每个凹部的表面上形成介电层。 然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。