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    PMOS transistor strain optimization with raised junction regions
    1.
    发明申请
    PMOS transistor strain optimization with raised junction regions 审中-公开
    具有凸起结区域的PMOS晶体管应变优化

    公开(公告)号：US20070034945A1

    公开(公告)日：2007-02-15

    申请号：US11586154

    申请日：2006-10-24

    申请人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    发明人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

    摘要： Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

    摘要翻译： PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。

    Integrated circuit with improved channel stress properties and a method for making it
    2.
    发明授权
    Integrated circuit with improved channel stress properties and a method for making it 失效
    具有改善的通道应力特性的集成电路及其制造方法

    公开(公告)号：US07045408B2

    公开(公告)日：2006-05-16

    申请号：US10443152

    申请日：2003-05-21

    申请人： Thomas Hoffmann ,  Chris Auth ,  Mark Armstrong ,  Stephen Cea

    发明人： Thomas Hoffmann ,  Chris Auth ,  Mark Armstrong ,  Stephen Cea

    IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L21/00 ,  H01L21/461 ,  H01L21/31

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/665

    摘要： An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

    摘要翻译： 描述了一种集成电路，其包括形成在半导体衬底上的PMOS晶体管和NMOS晶体管。 仅在PMOS晶体管或NMOS晶体管上形成硅酸盐玻璃层; 并且在硅酸盐玻璃层上形成蚀刻停止层。 还描述了一种用于形成集成电路的方法。 该方法包括在半导体衬底上形成PMOS晶体管结构和NMOS晶体管结构，仅在PMOS晶体管结构或NMOS晶体管结构上形成硅酸盐玻璃层，并在硅酸盐玻璃层上形成蚀刻停止层。

    Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
    7.
    发明申请
    Bulk non-planar transistor having strained enhanced mobility and methods of fabrication 有权
    具有应变增强的移动性和制造方法的散装非平面晶体管

    公开(公告)号：US20050224800A1

    公开(公告)日：2005-10-13

    申请号：US10816311

    申请日：2004-03-31

    申请人： Nick Lindert ,  Stephen Cea

    发明人： Nick Lindert ,  Stephen Cea

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/10

    CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78687

    摘要： A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 具有染色的增强迁移率的体三门极晶体管的方法及其制造方法。 本发明是具有应变增强迁移率的非平面晶体管及其制造方法。 晶体管具有形成在半导体衬底上的半导体本体，其中半导体本体在横向相对的侧壁上具有顶表面。 半导体盖层形成在半导体本体的顶表面和侧壁上。 在半导体本体的顶表面上的半导体覆盖层上形成栅介电层，并形成在半导体本体的侧壁上的覆盖层上。 具有一对横向相对的侧壁的栅电极形成在栅介质层上和周围。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。