公开(公告)号：US20070147118A1

公开(公告)日：2007-06-28

申请号：US11319260

申请日：2005-12-27

申请人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

发明人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07221008B2

公开(公告)日：2007-05-22

申请号：US10680665

申请日：2003-10-06

申请人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

发明人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

IPC分类号： H01L29/80 ,  H01L31/112 ,  H01L21/336 ,  G11C11/34 ,  G11C16/04

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from disturbs.

摘要翻译： 一种NAND闪速存储器结构和方法，其制造具有在位线方向上的屏蔽的闪存结构以及来自Yupin的字线和对角线方向的效果误差和干扰。

公开(公告)号：US20060227446A1

公开(公告)日：2006-10-12

申请号：US11100162

申请日：2005-04-06

申请人： Carl Elliott ,  Hao Fang ,  Ross Wilson

发明人： Carl Elliott ,  Hao Fang ,  Ross Wilson

IPC分类号： G11B20/10 ,  G11B21/02

CPC分类号： G11B20/1403 ,  G11B5/012 ,  G11B20/00086 ,  G11B20/0021 ,  G11B20/00579 ,  G11B20/10009 ,  G11B20/10425 ,  G11B2020/10898 ,  G11B2220/2516

摘要： A recording system stores recording cycle information identifying the parameters for recording user data on a particular data sector. During a subsequent operation, the recording system employs the recording cycle information to select a different set of parameters for recording new user data at the particular data sector. One of the parameters might identify a recorded pattern in a balance pad at the data sector, and another one of the parameters might identify a scrambler seed value. By employing a different set of recording parameters for each occurrence of recording user data at the particular sector, sample timing of, for example, a read channel might be based on an average of easy and hard transitions.

摘要翻译： 记录系统存储识别用于在特定数据扇区上记录用户数据的参数的记录周期信息。 在随后的操作期间，记录系统采用记录周期信息来选择用于在特定数据扇区记录新用户数据的不同参数集合。 参数中的一个可以识别数据扇区中的平衡衬垫中的记录模式，另一个参数可以识别加扰器种子值。 通过对特定扇区的记录用户数据的每次出现采用不同的记录参数集合，例如读通道的采样定时可以基于简单和硬转换的平均值。

公开(公告)号：US07019923B2

公开(公告)日：2006-03-28

申请号：US10420236

申请日：2003-04-22

申请人： John D. Leighton ,  Hao Fang ,  Michael J. O'Brien ,  Scott O'Brien ,  Cameron C. Rabe

发明人： John D. Leighton ,  Hao Fang ,  Michael J. O'Brien ,  Scott O'Brien ,  Cameron C. Rabe

IPC分类号： G11B5/09

CPC分类号： H03F3/45085

摘要： A pre-amplifier, a Thevenin writer and a disk drive employing transistors having a breakdown voltage below a circuitry operating voltage. In one embodiment, the pre-amplifier includes an emitter-follower transistor pair couplable to a power supply and a differential transistor pair, having a collector-emitter breakdown voltage below a voltage of the power supply, that receives current from, and controlled by, the emitter-follower transistor pair.

摘要翻译： 前置放大器，戴维南写入器和采用具有低于电路工作电压的击穿电压的晶体管的磁盘驱动器。 在一个实施例中，前置放大器包括可耦合到电源和差分晶体管对的发射极 - 跟随器晶体管对，其具有低于电源电压的集电极 - 发射极击穿电压，其接收来自并由其控制的电流， 射极跟随器晶体管对。

公开(公告)号：US20050072999A1

公开(公告)日：2005-04-07

申请号：US10680665

申请日：2003-10-06

申请人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

发明人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from distrubs.

摘要翻译： 一种NAND闪速存储器结构和方法，其制造具有在位线方向上的屏蔽的闪存结构以及来自Yupin效应误差和distrubs的字线和对角线方向。

公开(公告)号：US06602776B1

公开(公告)日：2003-08-05

申请号：US10155500

申请日：2002-05-23

申请人： Masaaki Higashitani ,  Hao Fang

发明人： Masaaki Higashitani ,  Hao Fang

IPC分类号： H01L2144

CPC分类号： H01L22/34

摘要： A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

公开(公告)号：US06514830B1

公开(公告)日：2003-02-04

申请号：US10044510

申请日：2002-01-11

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 一种制造高栅极二极管击穿电压，低泄漏和低体效应的高压晶体管的方法，同时避免过多数量的昂贵的掩蔽步骤。 在制造过程中通过掩蔽来自常规场注入的高压结和从常规阈值调整植入物屏蔽源极/漏极区域来提供高栅极二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06472327B2

公开(公告)日：2002-10-29

申请号：US09925205

申请日：2001-08-08

申请人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

发明人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

IPC分类号： H01L21304

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11534

摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

摘要翻译： 公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。 该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。 该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

公开(公告)号：US06351017B1

公开(公告)日：2002-02-26

申请号：US09533057

申请日：2000-03-22

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L31119

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结以及从常规阈值调整植入物屏蔽源/漏区来提供高门控二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06228782B1

公开(公告)日：2001-05-08

申请号：US09309994

申请日：1999-05-11

申请人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

发明人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76216 ,  H01L27/115

摘要： Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region. The high-energy implant also enhances isolation in the select transistor areas, thereby preventing an increase in device malfunctions, while the channel stop implant optimizes core field isolation.

摘要翻译： 选择性高能杂质注入使得能够优化核和外围场隔离，而不会显着降低功能性，自增强效率或以其他方式增加程序干扰，从而提高器件性能和可靠性。 实施例包括在半导体衬底中形成核心和外围场氧化物区域之后的高能杂质注入到对应于选择晶体管区域的外围场氧化物区域和核心场氧化物区域的选定部分，同时将核心存储器 细胞通道区。 在蚀刻第一多晶硅层之后，通过核心场氧化物区域进行沟道停止注入。 高能杂质注入优化外围场隔离，而不会降低自增强效率，因为它被阻止进入存储单元通道区。 高能量注入还增强了选择晶体管区域的隔离度，从而防止了器件故障的增加，而通道停止植入则优化了磁芯隔离。