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790 条记录 (耗时 0.046 秒)

    Business process enablement of electronic documents
    81.
    发明授权
    Business process enablement of electronic documents 有权
    业务流程启用电子文件

    公开(公告)号：US08201078B2

    公开(公告)日：2012-06-12

    申请号：US12211156

    申请日：2008-09-16

    申请人： John Boyer ,  Martin F. Dunn ,  Maureen E. Kraft ,  Jun Liu ,  Mihir R. Shah ,  He Feng Su ,  Saurabh Tiwari

    发明人： John Boyer ,  Martin F. Dunn ,  Maureen E. Kraft ,  Jun Liu ,  Mihir R. Shah ,  He Feng Su ,  Saurabh Tiwari

    IPC分类号： G06F17/00

    CPC分类号： G06Q10/00

    摘要： Business process enablement of electronic documents is provided. A method includes populating an electronic document supporting structured and unstructured content. The electronic document includes a description identifying a server and the content. The method further includes notifying a document processor of a submission event. The method also includes serializing a portion of the electronic document containing some of the unstructured content. The method additionally includes submitting the electronic document to the server in response to the submission event.

    摘要翻译： 提供电子文件的业务流程支持。 一种方法包括填充支持结构化和非结构化内容的电子文档。 电子文档包括标识服务器和内容的描述。 该方法还包括通知文档处理器提交事件。 该方法还包括串行化包含一些非结构化内容的电子文档的一部分。 该方法还包括响应于提交事件将电子文档提交给服务器。

    MEMORY DEVICES AND METHODS OF FORMING THE SAME
    82.
    发明申请
    MEMORY DEVICES AND METHODS OF FORMING THE SAME 有权
    记忆装置及其形成方法

    公开(公告)号：US20120135581A1

    公开(公告)日：2012-05-31

    申请号：US13369507

    申请日：2012-02-09

    申请人： Jun Liu

    发明人： Jun Liu

    IPC分类号： H01L21/8239

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

    摘要翻译： 具有多个存储单元的存储器件，每个存储单元包括具有横向收缩部分的相变材料。 相邻存储单元的横向收缩部分垂直偏移并且位于存储器件的相对侧上。 还公开了具有多个存储单元的存储器件，每个存储器单元包括具有不同宽度的第一和第二电极。 相邻存储器单元具有在存储器件的垂直相对侧上偏移的第一和第二电极。 还公开了形成存储器件的方法。

    SELF-ALIGNED, PLANAR PHASE CHANGE MEMORY ELEMENTS AND DEVICES, SYSTEMS EMPLOYING THE SAME AND METHODS OF FORMING THE SAME
    83.
    发明申请
    SELF-ALIGNED, PLANAR PHASE CHANGE MEMORY ELEMENTS AND DEVICES, SYSTEMS EMPLOYING THE SAME AND METHODS OF FORMING THE SAME 有权
    自对准的平面相变记忆元件和装置，使用它们的系统及其形成方法

    公开(公告)号：US20120132884A1

    公开(公告)日：2012-05-31

    申请号：US13364800

    申请日：2012-02-02

    申请人： Jun Liu

    发明人： Jun Liu

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

    摘要： Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane.

    摘要翻译： 公开了相变存储器元件，使用其的器件和系统及其形成方法。 存储元件包括第一和第二电极以及在第一和第二电极之间的相变材料层。 相变材料层具有宽度小于相变材料层的第二部分的宽度的第一部分。 第一电极，第二电极和相变材料层可以至少部分地沿着相同的水平面取向。

    Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell
    84.
    发明申请
    Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell 有权
    包含非易失性存储器单元的集成电路和形成非易失性存储器单元的方法

    公开(公告)号：US20120097913A1

    公开(公告)日：2012-04-26

    申请号：US12909650

    申请日：2010-10-21

    申请人： Jun Liu ,  John K. Zahurak

    发明人： Jun Liu ,  John K. Zahurak

    IPC分类号： H01L45/00 ,  H01L21/02

    CPC分类号： H01L45/1266 ,  H01L21/28114 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1691

    摘要： An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

    摘要翻译： 集成电路具有包括第一电极，第二电极和离子导电材料的非易失性存储单元。 第一和第二电极中的至少一个具有直接接受离子导电材料接受的电化学活性表面。 第二电极位于第一电极的正上方。 第一电极在第一方向上横向延伸，并且离子导电材料沿与第一方向不同并与第一方向相交的第二方向延伸。 仅在第一和第二方向相交的情况下，第一电极直接接收在离子导电材料上。 公开了包括方法实施例的其他实施例。

    Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
    85.
    发明授权
    Memory device constructions, memory cell forming methods, and semiconductor construction forming methods 有权
    存储器件结构，存储单元形成方法和半导体构造形成方法

    公开(公告)号：US08134137B2

    公开(公告)日：2012-03-13

    申请号：US12141388

    申请日：2008-06-18

    申请人： Jun Liu

    发明人： Jun Liu

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1608 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/6609 ,  H01L29/872

    摘要： Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.

    摘要翻译： 存储器件结构包括平行于第二列线延伸的第一列线，第一列线在第二列线之上; 在第二列线上方的行线，并垂直于第一列线和第二列线延伸; 存储器材料，其设置成选择性地和可逆地配置为两种或更多种不同电阻状态之一; 第一二极管，被配置为经由所述存储材料在所述第一列线和所述行线之间传导第一电流; 以及第二二极管，被配置为经由存储器材料在第二列线和行线之间传导第二电流。 在一些实施例中，第一二极管是具有半导体阳极和金属阴极的肖特基二极管，第二二极管是具有金属阳极和半导体阴极的肖特基二极管。

    Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
    86.
    发明申请
    Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices 有权
    存储单元，存储单元编程方法，存储单元读取方法，存储单元操作方法和存储器件

    公开(公告)号：US20120057391A1

    公开(公告)日：2012-03-08

    申请号：US13292680

    申请日：2011-11-09

    申请人： Jun Liu

    发明人： Jun Liu

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74

    摘要： Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

    摘要翻译： 所公开的实施例包括存储器单元操作方法，存储单元编程方法，存储单元读取方法，存储单元和存储器件。 在一个实施例中，存储器单元包括字线，第一位线，第二位线和存储器元件。 存储元件电连接到字线并选择性地电连接到第一位线和第二位线。 存储元件经由存储元件的电阻状态存储信息。 存储器单元被配置为经由从第一位线通过存储器元件流向字线的第一电流或从字线通过存储器元件流向第二位线的第二电流来传送存储器元件的电阻状态。

    Unidirectional spin torque transfer magnetic memory cell structure
    88.
    发明授权
    Unidirectional spin torque transfer magnetic memory cell structure 有权
    单向自旋转矩传递磁存储单元结构

    公开(公告)号：US08102700B2

    公开(公告)日：2012-01-24

    申请号：US12242261

    申请日：2008-09-30

    申请人： Jun Liu ,  Gurtej Sandhu

    发明人： Jun Liu ,  Gurtej Sandhu

    IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/02

    CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

    摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

    摘要翻译： 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

    Buck controller having integrated boost control and driver
    89.
    发明授权
    Buck controller having integrated boost control and driver 有权
    降压控制器具有集成升压控制和驱动器

    公开(公告)号：US08102162B2

    公开(公告)日：2012-01-24

    申请号：US12482818

    申请日：2009-06-11

    申请人： Zaki Moussaoui ,  Leigh Cormie ,  Jun Liu

    发明人： Zaki Moussaoui ,  Leigh Cormie ,  Jun Liu

    IPC分类号： G05F1/563

    CPC分类号： H02M3/1582

    摘要： An integrated circuit controller for controlling the operation of a voltage converter which includes a first comparator for comparing a voltage associated with an input of a boost converter with a threshold voltage and generating a control signal in response thereto. A second comparator compares a second voltage associated with an output of the boost converter with the threshold voltage and generates a second control signal in response thereto. Driver circuitry generates a first switching transistor drive signal and a second switching transistor drive signal. The first switching transistor drive signal is used for driving an upper gate switching transistor of a buck converter. The second switching transistor drive signal may be configured in a first mode of operation to drive a lower gate switching transistor of the buck converter and may be configured in a second mode of operation to drive a switching transistor of the boost converter. Control logic enables/disables at least a portion of the driver circuitry responsive to the control signal and the second control signal.

    摘要翻译： 一种用于控制电压转换器的操作的集成电路控制器，其包括用于将与升压转换器的输入相关联的电压与阈值电压进行比较的第一比较器，并响应于此产生控制信号。 第二比较器将与升压转换器的输出相关联的第二电压与阈值电压进行比较，并响应于此产生第二控制信号。 驱动器电路产生第一开关晶体管驱动信号和第二开关晶体管驱动信号。 第一开关晶体管驱动信号用于驱动降压转换器的上栅极开关晶体管。 第二开关晶体管驱动信号可以被配置为第一操作模式以驱动降压转换器的下栅极开关晶体管，并且可以被配置为驱动升压转换器的开关晶体管的第二操作模式。 响应于控制信号和第二控制信号，控制逻辑启用/禁用至少一部分驱动器电路。

    MEMORY CELLS WITH RECTIFYING DEVICE
    90.
    发明申请
    MEMORY CELLS WITH RECTIFYING DEVICE 有权
    具有修复装置的记忆细胞

    公开(公告)号：US20110255331A1

    公开(公告)日：2011-10-20

    申请号：US13158836

    申请日：2011-06-13

    申请人： Jun Liu

    发明人： Jun Liu

    IPC分类号： G11C11/21

    CPC分类号： G11C13/0004 ,  C07D213/81 ,  C07D401/06 ,  C07D401/12 ,  C07D401/14 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/1021

    摘要： Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

    摘要翻译： 显示了所描述的存储器件和方法，其提供了改进，包括改进的诸如读取和写入等操作的单元隔离。 此外，示出了用于寻址和访问单元的方法和设备，其提供用于管理具有与每个存取晶体管相关联的多个单元的器件的简单且有效的方式。 多个单元设备的示例包括具有与每个存取晶体管相关联的多个单元的相变存储器件。