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公开(公告)号：US11449377B2
公开(公告)日：2022-09-20
申请号：US16996267
申请日：2020-08-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号：US20250118364A1
公开(公告)日：2025-04-10
申请号：US18988243
申请日：2024-12-19
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Tingjun Xie , Jiangli Zhu , Nagendra Prasad Ganesh Rao , Sead Zildzic
IPC: G11C11/56
Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.
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公开(公告)号：US20250111886A1
公开(公告)日：2025-04-03
申请号：US18979331
申请日：2024-12-12
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20250104772A1
公开(公告)日：2025-03-27
申请号：US18971520
申请日：2024-12-06
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Murong Lang , Fangfang Zhu , Jiangli Zhu , Zhenming Zhou
Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.
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公开(公告)号：US12260916B2
公开(公告)日：2025-03-25
申请号：US18404827
申请日：2024-01-04
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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Patent Agency Ranking
公开(公告)号：US12216529B2
公开(公告)日：2025-02-04
申请号：US17933443
申请日：2022-09-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号：US20240420784A1
公开(公告)日：2024-12-19
申请号：US18739769
申请日：2024-06-11
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Peng Zhang , Lei Lin , Zhenming Zhou , Jun Wan
Abstract: Aspects of the present disclosure configure a memory sub-system controller to selectively adjust a program pulse for different word line groups of a memory sub-system. The controller receives a request to program data to an individual memory component of a set of memory components. The controller determines that a program erase count (PEC) associated with the individual memory component transgresses a threshold value. The controller, in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusts a predetermined program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG). The controller programs the data to the individual memory component according to the selectively adjusted predetermined Vpgm.
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公开(公告)号：US12165709B2
公开(公告)日：2024-12-10
申请号：US17876346
申请日：2022-07-28
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Murong Lang , Fangfang Zhu , Jiangli Zhu , Zhenming Zhou
Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.
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公开(公告)号：US20240386972A1
公开(公告)日：2024-11-21
申请号：US18787787
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Murong Lang , Li-Te Chang
IPC: G11C16/34 , G11C11/406
Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.
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90.发明申请公开(公告)号：US20240371450A1
公开(公告)日：2024-11-07
申请号：US18637412
申请日：2024-04-16
Applicant: Micron Technology, Inc.
Inventor： Peng Zhang , Lei Lin , Zhengang Chen , Murong Lang , Zhenming Zhou
Abstract: A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.
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