公开(公告)号：US06222230B1

公开(公告)日：2001-04-24

申请号：US09204967

申请日：1998-12-03

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L2976

CPC分类号： H01L29/66621 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823487 ,  H01L29/4232 ,  H01L29/4238

摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.

摘要翻译： 提供集成电路及其制造晶体管的方法。 在一个方面，集成电路包括基板和位于基板的多个有源区上的多个晶体管。 每个晶体管具有位于衬底中的掺杂区域，位于衬底中的锥形沟槽中的绝缘层，其延伸穿过并将掺杂区域划分为第一源极/漏极区域和第二源极/漏极区域。 绝缘层是具有基部的沟道形状，第一向上倾斜的侧壁和第二向上倾斜的侧壁。 栅电极位于绝缘层上。 通道形栅极电介质层需要较少的水平衬底面积，使给定衬底具有更高的堆积密度。 倾斜的侧壁作为间隔件加倍，使工艺简化。

公开(公告)号：US06188110B1

公开(公告)日：2001-02-13

申请号：US09173015

申请日：1998-10-15

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L29796

CPC分类号： H01L21/823807 ,  Y10S257/90

摘要： A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

摘要翻译： 形成集成隔离区域和有源区域的方法包括首先在半导体衬底上形成多个电介质层。 然后，施加图案化掩模以限定将保留形成隔离区域的部分介电层，并且限定将在蚀刻步骤中去除以在半导体衬底的表面产生空隙的电介质层的部分。 随后，使用外延生长在预先形成的空隙内形成活性区。 然后在有源区上形成晶体管，然后将其互连形成集成电路。

公开(公告)号：US06188106B1

公开(公告)日：2001-02-13

申请号：US09146410

申请日：1998-09-03

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： H01L2978

CPC分类号： H01L29/51 ,  H01L21/26533 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/665 ,  H01L29/6659

摘要： A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthrough. A barrier layer is then formed between the liner layer and the upper surface of the semiconductor substrate. The barrier layer preferably inhibits migration of the liner ions into the junction and channel regions of the transistors during subsequent processing steps. Such migration could deleteriously affect transistor function by, e.g., increasing the threshold voltage and thus decreasing the drive current. The barrier layer also preferably facilitates formation of shallow junctions. In an embodiment, the liner layer may include p-type ions such as boron and the barrier layer may include nitrogen implanted into the semiconductor substrate. Alternatively, the barrier layer may include nitrogen-incorporated epitaxially grown silicon.

摘要翻译： 提供一种制造工艺和集成电路，其中形成具有增加的穿透电阻和降低的沟道电容的晶体管。 在晶体管的有源区内形成衬垫层以最小化穿透。 然后在衬垫层和半导体衬底的上表面之间形成阻挡层。 阻挡层优选地在随后的处理步骤期间抑制衬里离子迁移到晶体管的结和沟道区中。 这种迁移可以通过例如增加阈值电压并从而降低驱动电流来有害地影响晶体管功能。 阻挡层还优选有利于形成浅结。 在一个实施例中，衬垫层可以包括诸如硼的p型离子，并且阻挡层可以包括注入到半导体衬底中的氮。 或者，阻挡层可以包括掺入氮的外延生长的硅。

公开(公告)号：US06184566B2

公开(公告)日：2001-02-06

申请号：US09150776

申请日：1998-09-10

申请人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

IPC分类号： H01L2176

CPC分类号： H01L21/823418 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823481 ,  Y10S257/90

摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

摘要翻译： 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括横向移位的源极/漏极区域和沟道区域。 第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。 第一和第二晶体管具有公共源极/漏极区域。 通过公共源极/漏极区形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与 第二晶体管。

公开(公告)号：US6159804A

公开(公告)日：2000-12-12

申请号：US145663

申请日：1998-09-02

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/72

CPC分类号： H01L29/66659 ,  H01L21/28132 ,  H01L21/823425 ,  H01L21/823468

摘要： The present invention is directed to a method of making a transistor having a very short channel length. The method generally comprises forming a plurality of process layers above a surface of a semiconducting substrate, one of the process layers being comprised of a gate dielectric material and another of the process layers being comprised of a gate conductor material. The method further comprises patterning the plurality of process layers to define an opening and forming a first sidewall spacer in the opening adjacent at least the process layer comprised of a gate conductor material. The method continues with the formation of a gate conductor mask by oxidation of a portion of at least one of the process layers other than those layers comprised of a gate dielectric material and the gate conductor material. A portion of the process layer comprised of a gate conductor material is then removed to define a gate conductor positioned beneath the gate conductor mask, followed by the formation of a second sidewall spacer adjacent the gate conductor. Thereafter, at least one source/drain region is formed to complete the transistor formation. The present invention further comprises a transistor having a channel length of less than 1000 .ANG..

摘要翻译： 本发明涉及一种制造具有非常短的通道长度的晶体管的方法。 该方法通常包括在半导体衬底的表面上方形成多个工艺层，其中一个工艺层由栅极电介质材料构成，另一个工艺层由栅极导体材料构成。 该方法还包括对多个处理层进行图案化以限定开口，并且在开口中形成邻近至少由栅极导体材料构成的工艺层的第一侧壁间隔物。 该方法继续通过除了由栅极电介质材料和栅极导体材料构成的那些层之外的至少一个工艺层的一部分的氧化形成栅极导体掩模。 然后移除由栅极导体材料构成的工艺层的一部分，以限定位于栅极导体掩模下方的栅极导体，随后形成邻近栅极导体的第二侧壁间隔物。 此后，形成至少一个源极/漏极区以完成晶体管的形成。 本发明还包括具有小于1000安培的通道长度的晶体管。

公开(公告)号：US6121099A

公开(公告)日：2000-09-19

申请号：US192123

申请日：1998-11-13

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/7835 ,  Y10S438/91

摘要： A semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls on the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate includes a first and a second sidewall. Exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement. A channel boundary of the first source region is laterally displaced from the second sidewall of the conductive gate by the source displacement. Exterior sidewalls of the second pair of spacer structures are laterally displaced from the first and second sidewalls of the conductive gate by a drain displacement. A channel boundary of the detached drain region is laterally displaced from the first sidewall of the conductive gate by the drain displacement. The conductive gate may comprise heavily doped CVD polysilicon or, alternatively, the conductive gate may be formed from a metal such as aluminum, copper, tungsten, or alloys thereof.

摘要翻译： 一种半导体制造方法，包括提供半导体衬底，在所述半导体衬底的上表面上形成栅极电介质，在所述栅极电介质的上表面上形成导电栅极，在所述第一和第二侧壁上形成第一对间隔结构， 所述导电栅极将第一源杂质分布引入到所述半导体衬底中，在所述第一对间隔结构的相应外侧壁上形成第二对间隔结构，并将漏极杂质分布引入所述半导体衬底的所述脱离的漏极区。 半导体衬底包括在第一源极区域和脱离漏极区域之间横向移位的沟道区域。 导电栅极包括第一和第二侧壁。 第一对间隔结构的外侧壁通过源位移从导电栅极的第一和第二侧壁位移。 第一源极区的沟道边界通过源极位移从导电栅极的第二侧壁横向移位。 第二对间隔结构的外侧壁通过排水位移从导电门的第一和第二侧壁横向移位。 分离漏极区域的通道边界通过排水位移从导电栅极的第一侧壁横向移位。 导电栅极可以包括重掺杂的CVD多晶硅，或者，导电栅极可以由诸如铝，铜，钨或其合金的金属形成。

公开(公告)号：US6117760A

公开(公告)日：2000-09-12

申请号：US968682

申请日：1997-11-12

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Fred N. Hause

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Fred N. Hause

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects. A conductive material is then deposited across into a trench arranged between the first and second interconnects, and CMP polished such that the upper surface of the conductive material is at an elevational level proximate that of the surfaces of the interconnects. A third interconnect is thereby formed within the trench laterally adjacent the first and second interconnects.

摘要翻译： 提供了一种技术，用于通过沉积的介电隔离层在半导体形貌上形成横向间隔开的互连。 每个互连之间的横向距离有利地由隔离层的厚度而不是光刻图案化掩模层的最小特征尺寸决定。 在一个实施例中，第一和第二导电互连在半导体形貌上分开形成间隔距离。 第一和第二互连使用光刻和蚀刻技术来定义。 介电层是跨越第一和第二互连的暴露表面和半导体形貌的CVD沉积的。 控制CVD沉积条件以形成横向邻近互连侧壁的较薄的间隔件。 然后将导电材料沉积到布置在第一和第二互连之间的沟槽中，并且CMP抛光，使得导电材料的上表面处于靠近互连表面的上表面。 因此，在沟槽内形成第三互连件，横向地邻近第一和第二互连。

公开(公告)号：US6111260A

公开(公告)日：2000-08-29

申请号：US872258

申请日：1997-06-10

申请人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01J37/317

CPC分类号： H01J37/3171 ,  H01J2237/316

摘要： During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.

摘要翻译： 在半导体衬底离子注入过程中，提供热能以提高半导体晶片的温度。 在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂，减少杂质扩散并减少制造工艺步骤的数量。 离子注入装置包括终端站，其适于向端站施加和控制热能，以在植入期间提高半导体衬底晶片的温度。 适用的端站包括用于加热半导体衬底晶片的加热元件，用于感测半导体衬底晶片的温度的热电偶，以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器 。 包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度 晶片，但当离子束无效时，温度不足以激活杂质。

公开(公告)号：US6107129A

公开(公告)日：2000-08-22

申请号：US38511

申请日：1998-03-11

申请人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/6659 ,  H01L29/7833 ,  H01L29/7835

摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.

摘要翻译： 形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。 晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。 多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。 因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

公开(公告)号：US6091105A

公开(公告)日：2000-07-18

申请号：US50753

申请日：1998-03-30

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/66666 ,  H01L29/7827

摘要： An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.

摘要翻译： 提供一种集成电路及其制造方法。 在衬底中形成沟槽。 沟槽有侧壁。 在侧壁上形成第一绝缘层。 在第一绝缘层上形成栅电极。 在衬底中形成第一源极/漏极区域，并且在衬底中形成第二源极/漏极区域。 第一源极/漏极区域的第一部分和第二源极/漏极区域的第二部分垂直间隔开以限定衬底中的沟道区域。 该过程使得通道长度被设置为独立于用于图案化晶片的光刻系统的最大分辨率。 可以实现非常短的通道长度。