公开(公告)号：US5858848A

公开(公告)日：1999-01-12

申请号：US957090

申请日：1997-10-24

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/336

CPC分类号： H01L29/66583 ,  Y10S257/90

摘要： A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate. A dielectric, preferably nitride, is deposited by CVD across the exposed LDD areas of the semiconductor substrate, the sacrificial dielectric, and the gate conductor. The nitride is removed down to a plane level with the upper surface of the gate conductor. The sacrificial dielectric may then be removed from the semiconductor substrate. An ion implantation which is self-aligned to exposed lateral edges of the spacers may then be performed to form heavily doped source/drain regions laterally spaced from the channel.

公开(公告)号：US5851888A

公开(公告)日：1998-12-22

申请号：US784195

申请日：1997-01-15

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31111 ,  H01L29/518 ,  H01L21/02052 ,  H01L21/28238

摘要： A method for fabrication a gate dielectric in which an initial dielectric layer comprising a sacrificial portion and a permanent portion is formed on the semiconductor substrate. Thereafter the sacrificial portion is controllably removed with an etchback process. The gate dielectric is preferably comprised of oxynitride to reduce boron penetration from the conductive gate into the transistor channel region and the gate dielectric has a final thickness less than approximately 30 angstroms. The method includes providing a semiconductor substrate having channel region that is laterally displaced between a pair of source/drain regions. An upper surface of said semiconductor substrate is then cleaned and the semiconductor substrate is loaded into an oxidation chamber containing a first ambient maintained at a first temperature for a first duration to grow an initial dielectric layer over the channel region of said semiconductor substrate. The first ambient includes a nitrogen bearing species, and the initial dielectric layer includes a sacrificial portion formed over a permanent portion. A gate dielectric is then formed by etching back the initial dielectric layer at a first etch rate to remove said sacrificial portion of the gate dielectric over the channel region. The gate dielectric is then annealed in an inert ambient maintained at an anneal temperature for an anneal duration. Thereafter, a conductive gate structure is formed on the gate dielectric aligned over the channel region of the semiconductor substrate and a pair of s/d structures are formed in a pair of s/d regions respectively of said semiconductor substrate. The pair of s/d regions are laterally displaced on either side of the channel region of the semiconductor substrate.

摘要翻译： 一种用于制造栅极电介质的方法，其中在半导体衬底上形成包括牺牲部分和永久部分的初始电介质层。 此后，通过回蚀工艺可控地去除牺牲部分。 栅电介质优选由氧氮化物组成，以减少从导电栅极渗入晶体管沟道区域的硼渗透，并且栅极电介质的最终厚度小于约30埃。 该方法包括提供具有在一对源极/漏极区之间横向移位的沟道区的半导体衬底。 然后清洁所述半导体衬底的上表面，并将半导体衬底装载到含有保持在第一温度的第一环境的氧化室中，持续第一时间，以在所述半导体衬底的沟道区上生长初始介电层。 第一环境包括含氮物质，并且初始介电层包括在永久部分上形成的牺牲部分。 然后通过以第一蚀刻速率蚀刻回初始介电层以去除沟道区上的栅极电介质的所述牺牲部分来形成栅极电介质。 然后将栅电介质在保持退火温度的惰性环境中退火退火持续时间。 此后，在半导体衬底的沟道区上对齐的栅极电介质上形成导电栅极结构，并且在所述半导体衬底的一对s / d区中形成一对s / d结构。 一对s / d区域在半导体衬底的沟道区域的两侧被横向移位。