公开(公告)号：US5475266A

公开(公告)日：1995-12-12

申请号：US342400

申请日：1994-11-18

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/53257 ,  H01L21/76886 ,  H01L23/485 ,  H01L2924/0002

Abstract: A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.

Abstract translation: 微电子器件（10）提供减少的条形面积的使用以在导电带（24）或互连和随后的级之间形成接触。 导电带包括导电层（130）和上覆半导体层（132）。 通常覆盖衬底导电区域（例如门（14）和/或护城河（16））与后续层的连接。 通过掺杂上覆的半导体子层（132）来实现与导电子层（130）的连接。 衬底导电区域的任何反掺杂被掺杂剂掩蔽（33）或足够厚的半导体（32）材料的上覆阱阻挡。

公开(公告)号：US5231296A

公开(公告)日：1993-07-27

申请号：US788973

申请日：1991-11-07

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66765 ,  H01L21/28 ,  H01L29/78618

Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.

Abstract translation: 公开了一种薄膜晶体管及其形成方法。 晶体管包括栅极导体（14）和栅极绝缘体（16）。 在栅极绝缘体（16）附近形成半导体沟道层（18）。 掩模块（22）被形成为覆盖沟道层（18）中的沟道区（30）。 源极区域（26）和漏极区域（28）形成在与掩模块（22）的相对端相邻的沟道层（18）中。 导电体（32）和（34）分别形成为与源区（26）和漏区（28）接触。 然后，电触点（42）和（44）分别与导电体（32）和（34）接触形成。

公开(公告)号：US5213990A

公开(公告)日：1993-05-25

申请号：US861688

申请日：1992-04-01

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6659 ,  H01L21/28525 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66628 ,  H01L2924/0002 ,  Y10S148/053 ,  Y10S148/109 ,  Y10S438/906

Abstract: A method for connecting different conducting layers of a microelectronic device is disclosed. The method comprises: providing a first conducting layer (40); forming a first insulating layer (42) over said first conducting layer (40); forming a second conducting layer over said first insulating layer (42); patterning said second conducting layer to form a conducting element (44) over said first insulating layer (42) whereby the top surface of said first insulating layer (42) is protected from deleterious effects of further process steps; forming a second insulating layer (46) over said conducting element (44) and said first insulating layer (42) selectively removing said first insulating layer (42) and said second insulating layer (46), using an etch process which is selective over said insulating layers (42, 46) said conducting element (44) and said first conducting layer (40), to form a contact region (48) which straddles an edge of said conducting element (44) such that a portion of said conducting element (44) is exposed adjacent to an exposed portion of said conducting layer (40) with said first insulating layer (42) vertically interposed; and forming a third conducting layer (50) within said contact area (48). Other methods are also disclosed.

Abstract translation: 公开了一种用于连接微电子器件的不同导电层的方法。 该方法包括：提供第一导电层（40）; 在所述第一导电层（40）上形成第一绝缘层（42）; 在所述第一绝缘层（42）上形成第二导电层; 图案化所述第二导电层以在所述第一绝缘层（42）上形成导电元件（44），从而保护所述第一绝缘层（42）的顶表面免受进一步处理步骤的有害影响; 在所述导电元件（44）和所述第一绝缘层（42）上形成第二绝缘层（46），所述第二绝缘层选择性地去除所述第一绝缘层（42）和所述第二绝缘层（46） 绝缘层（42,46），所述导电元件（44）和所述第一导电层（40），以形成跨越所述导电元件（44）的边缘的接触区域（48），使得所述导电元件 44）与所述导电层（40）的暴露部分相邻地露出，所述第一绝缘层（42）垂直插入; 以及在所述接触区域（48）内形成第三导电层（50）。 还公开了其它方法。

公开(公告)号：US5198378A

公开(公告)日：1993-03-30

申请号：US609969

申请日：1990-12-10

Applicant: Mark S. Rodder ,  Richard A. Chapman

Inventor： Mark S. Rodder ,  Richard A. Chapman

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L21/76889 ,  H01L29/41775 ,  H01L29/78 ,  Y10S257/90

Abstract: An elevated transistor is provided having minimized junctions (33) and a polysilicon pad (27) over the transistor insulating regions (12) and partially over the moat (14). A conductive layer (32) overlays the polysilicon pad (27) and partially overlays the moat (14) in the interim areas (29).

Abstract translation: 在晶体管绝缘区域（12）上并部分地在护城河（14）之上提供了具有最小结（33）和多晶硅焊盘（27）的升高的晶体管。 导电层（32）覆盖多晶硅垫（27）并部分覆盖中间区域（29）中的护城河（14）。

公开(公告)号：US5192706A

公开(公告)日：1993-03-09

申请号：US575259

申请日：1990-08-30

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/308 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/76229 ,  Y10S148/127

Abstract: This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.

Abstract translation: 这是一种形成半导体集成电路的方法，该半导体集成电路具有包括薄氧化膜和沉积的各向异性氧化物的隔离区（可能宽和窄）。 它使用无机层（例如非晶硅）来掩蔽将是有效区域并且允许在沟槽中生长热氧化膜以减少沿着沟槽的寄生通道形成。 使用各向异性氧化物填充沟槽允许宽且窄的沟槽被同时填充到期望的深度。 去除无机层和使用各向异性氧化物填充沟槽会产生平坦的平面和更细的隔离区。

公开(公告)号：US5100816A

公开(公告)日：1992-03-31

申请号：US556232

申请日：1990-07-20

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66765 ,  H01L29/78624

Abstract: A transistor is disclosed which comprises a gate conductor 34 insulated from a channel region 55 by a gate insulator layer 38. A spacer insulator block 46 is used to accurately space a drain region 52 a predetermined distance from the gate conductor 34. A dopant source body 48 is used to form the drain region 52 such that the formation of the drain region 52 is a self-aligned process. According to the teachings of the present invention, the drain region 52 can be accurately spaced from the gate conductor 34 to reduced field enhanced leakage current during the operation of the transistor.

Abstract translation: 公开了一种晶体管，其包括通过栅极绝缘体层38与沟道区55绝缘的栅极导体34.间隔绝缘体块46用于将距离栅极导体34预定距离的漏极区域52精确地间隔开。掺杂剂源体 48用于形成漏区52，使得漏区52的形成是自对准工艺。 根据本发明的教导，在晶体管的操作期间，漏区52可以与栅极导体34精确地间隔开，以减小场增强的漏电流。