公开(公告)号：US20220261363A1

公开(公告)日：2022-08-18

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

公开(公告)号：US20220246220A1

公开(公告)日：2022-08-04

申请号：US17726351

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenszo ,  Daniele Balluchi

IPC: G11C16/30 ,  G11C16/04

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

公开(公告)号：US20220197564A1

公开(公告)日：2022-06-23

申请号：US17550297

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

公开(公告)号：US20220179736A1

公开(公告)日：2022-06-09

申请号：US17541956

申请日：2021-12-03

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F11/10

Abstract: Systems, apparatuses, and methods related to modified parity data using a poison data unit. An example method can include receiving, from a controller of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits comprises one or more erroneous or corrupted bits. The method can further include generating, at an encoder of the memory device, parity data associated with the first set of bits. The method can further include generating, at logic of the memory device, modified parity data with the parity data component and the second set of at least one bit. The method can further include writing the first set of bits and the modified parity data in an array of the memory device.

公开(公告)号：US20210406203A1

公开(公告)日：2021-12-30

申请号：US16963110

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F12/10 ,  G06F12/121

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

公开(公告)号：US20210319829A1

公开(公告)日：2021-10-14

申请号：US16846481

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

IPC: G11C13/00

Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

公开(公告)号：US11132311B2

公开(公告)日：2021-09-28

申请号：US16702980

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US10956290B2

公开(公告)日：2021-03-23

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US10809942B2

公开(公告)日：2020-10-20

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

公开(公告)号：US20200081853A1

公开(公告)日：2020-03-12

申请号：US16128882

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Marco Dallabora ,  Daniele Balluchi ,  Paolo Amato ,  Luca Porzio

IPC: G06F13/16 ,  G06F13/28

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.