公开(公告)号：US10417236B2

公开(公告)日：2019-09-17

申请号：US16204677

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06F13/28 ,  G06F16/2455 ,  G06F13/42

Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

公开(公告)号：US10380446B2

公开(公告)日：2019-08-13

申请号：US15967176

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Steven P. King

IPC: G06F13/40 ,  G06K9/00 ,  G06F16/9032

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

公开(公告)号：US10372653B2

公开(公告)日：2019-08-06

申请号：US16053562

申请日：2018-08-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F15/18 ,  G06F13/40 ,  G06F15/78 ,  G06F9/448 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20190235766A1

公开(公告)日：2019-08-01

申请号：US16376881

申请日：2019-04-05

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F3/06 ,  G06N3/02 ,  G06F8/41

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0673 ,  G06F8/42 ,  G06N3/02

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US10254976B2

公开(公告)日：2019-04-09

申请号：US15206824

申请日：2016-07-11

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/312 ,  G06F3/06 ,  G06F8/41 ,  G06N3/02

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20190095496A1

公开(公告)日：2019-03-28

申请号：US16204677

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06F17/30 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F16/24568 ,  G06F13/28 ,  G06F13/4282

Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

公开(公告)号：US10162862B2

公开(公告)日：2018-12-25

申请号：US15208419

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06F13/42 ,  G06F17/30 ,  G06F13/28

Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

公开(公告)号：US20180137416A1

公开(公告)日：2018-05-17

申请号：US15871660

申请日：2018-01-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06N3/08 ,  G06N3/063 ,  G06K9/00

CPC classification number: G06N3/08 ,  G06K9/00986 ,  G06N3/063

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US20180089113A1

公开(公告)日：2018-03-29

申请号：US15280611

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20170193351A1

公开(公告)日：2017-07-06

申请号：US14984955

申请日：2015-12-30

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: G06N3/04 ,  G06K9/00 ,  G06K9/62

CPC classification number: G06K9/00973 ,  G06N5/02

Abstract: An apparatus includes a state machine lattice. The apparatus also includes a memory. The memory of the apparatus is configured to receive an event vector, such that the event vector includes an indication of a result of data analysis using the state machine lattice. The apparatus further includes a control system. The control system of the apparatus is configured to selectively provide only a portion of the event vector.