公开(公告)号：US20220384645A1

公开(公告)日：2022-12-01

申请号：US17886436

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L29/10

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

公开(公告)号：US11171148B2

公开(公告)日：2021-11-09

申请号：US16527552

申请日：2019-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11573

Abstract: Integrated circuits, and integrated circuit devices, might include a semiconductor, a first active area in the semiconductor, a second active area in the semiconductor, and an isolation structure in the semiconductor between the first active area and the second active area. The isolation structure might include a first edge portion extending below a surface of the semiconductor to a first depth, a second edge portion extending below the surface of the semiconductor to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor to a second depth, less than the first depth.

公开(公告)号：US10325847B2

公开(公告)日：2019-06-18

申请号：US15865819

申请日：2018-01-09

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L29/76 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

公开(公告)号：US10290575B2

公开(公告)日：2019-05-14

申请号：US15885086

申请日：2018-01-31

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US20180294194A1

公开(公告)日：2018-10-11

申请号：US16007139

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

公开(公告)号：US20180174960A1

公开(公告)日：2018-06-21

申请号：US15885086

申请日：2018-01-31

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US20170110402A1

公开(公告)日：2017-04-20

申请号：US15393553

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US20170069538A1

公开(公告)日：2017-03-09

申请号：US15357602

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路。 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有效区域。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

公开(公告)号：US09287260B1

公开(公告)日：2016-03-15

申请号：US14478220

申请日：2014-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: H01L27/088 ,  H01L27/115 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

Abstract translation: 在一个实施例中，晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上，以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。

公开(公告)号：US20150214107A1

公开(公告)日：2015-07-30

申请号：US14679488

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L27/115 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract translation: 公开了用于形成半导体结构的方法，包括形成导电材料和绝缘材料组的方法，在组上形成第一掩模，形成第一数量的接触区域，在组的第一区域上形成第二掩模， 以及在与所述第一区域横向相邻的第二暴露区域中从所述组中移除材料以形成第二数量的接触区域。 另一种方法包括在导电材料和绝缘材料组的部分上形成第一和第二接触区域，每个第二接触区域比每个第一接触区域更靠近下面的衬底。 还公开了诸如包括横向相邻的第一和第二区域的存储器件的装置，每个区域包括多个导电材料的不同部分的接触区域和形成这种器件的相关方法。