公开(公告)号：US12274057B2

公开(公告)日：2025-04-08

申请号：US18533291

申请日：2023-12-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith

IPC: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.

公开(公告)号：US12015026B2

公开(公告)日：2024-06-18

申请号：US17473285

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/22 ,  G11C16/26 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/06 ,  H10B41/40 ,  H10B43/40

CPC classification number: H01L27/0266 ,  G11C16/22 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/3212 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0649 ,  H10B41/40 ,  H10B43/40 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/31116 ,  H01L21/32137

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US20240072057A1

公开(公告)日：2024-02-29

申请号：US17898184

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L27/0928 ,  H01L21/823857 ,  H01L21/823892 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42364

Abstract: Semiconductor devices including an adjusted bottom/deep well embedded in a semiconductor substrate. The adjusted bottom/deep well having one or more characteristics resulting from being formed using or through a temporary masked layer.

公开(公告)号：US20230395159A1

公开(公告)日：2023-12-07

申请号：US18315311

申请日：2023-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kunal R. Parekh ,  Hernan A. Castro

IPC: G11C16/24 ,  H10B43/40 ,  H10B43/10 ,  G11C16/16

CPC classification number: G11C16/24 ,  H10B43/40 ,  H10B43/10 ,  G11C16/16 ,  G11C16/0483

Abstract: Interfaces between higher voltage and lower voltage wafers and related apparatuses and methods are disclosed. An apparatus includes a memory wafer and a logic wafer. Data storage elements of an array are configured to perform an operation responsive to an operational voltage potential. The memory wafer also includes bitlines electrically connected to the data storage elements and isolation devices electrically connected to the bitlines. The logic wafer is bonded to the memory wafer. The logic wafer includes logic circuitry electrically connected to the bitlines through the isolation devices. A maximum voltage potential difference tolerance of the logic circuitry is less than an operational voltage potential difference between the operational voltage potential and a reference voltage potential of the logic circuitry. A method includes isolating the logic circuitry from the bitlines, applying the operational voltage potential the data storage elements, and electrically connecting the logic circuitry to the bitlines.

公开(公告)号：US11790995B2

公开(公告)日：2023-10-17

申请号：US17400924

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/735

CPC classification number: G11C16/14 ,  G11C16/0483 ,  H01L29/735

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

公开(公告)号：US20230046480A1

公开(公告)日：2023-02-16

申请号：US17400924

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: G11C16/14 ,  G11C16/04 ,  H01L29/735

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

公开(公告)号：US20220320351A1

公开(公告)日：2022-10-06

申请号：US17807831

申请日：2022-06-20

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/94 ,  H01L29/49 ,  H01L21/28 ,  G11C16/30 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/66

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

公开(公告)号：US20220149199A1

公开(公告)日：2022-05-12

申请号：US17095475

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L29/10

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

公开(公告)号：US10431577B2

公开(公告)日：2019-10-01

申请号：US15892625

申请日：2018-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/115 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/28 ,  H01L21/3213 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/311

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US20190267322A1

公开(公告)日：2019-08-29

申请号：US16413470

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11556

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.