公开(公告)号：US20210066328A1

公开(公告)日：2021-03-04

申请号：US16552257

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Albert Fayrushin ,  Haitao Liu ,  Kirk D. Prall

IPC: H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.

公开(公告)号：US20210043731A1

公开(公告)日：2021-02-11

申请号：US16986436

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210035979A1

公开(公告)日：2021-02-04

申请号：US17065711

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/28

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

公开(公告)号：US20200350440A1

公开(公告)日：2020-11-05

申请号：US16401844

申请日：2019-05-02

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Kamal M. Karda ,  Stephen J. Kramer ,  Gurtej S. Sandhu ,  Sumeet C. Pandey ,  Haitao Liu

IPC: H01L29/786 ,  H01L29/16 ,  H01L51/05 ,  G11C13/00

Abstract: A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

公开(公告)号：US10818666B2

公开(公告)日：2020-10-27

申请号：US16291597

申请日：2019-03-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/285 ,  H01L21/28

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

公开(公告)号：US20200286899A1

公开(公告)日：2020-09-10

申请号：US16294792

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

公开(公告)号：US10756093B1

公开(公告)日：2020-08-25

申请号：US16294792

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  H01L25/18 ,  H01L29/417 ,  G11C11/407

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

公开(公告)号：US10748931B2

公开(公告)日：2020-08-18

申请号：US15974141

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200258887A1

公开(公告)日：2020-08-13

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US20200227417A1

公开(公告)日：2020-07-16

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/167 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.