公开(公告)号：US06506650B1

公开(公告)日：2003-01-14

申请号：US09843782

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66598 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/6656 ,  H01L29/6659

Abstract: A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.

Abstract translation: 描述了一种MOSFET晶体管及其制造方法，用于通过单个深度注入步骤和固相外延来在MOSFET晶体管内工程化沟道掺杂物分布。 该方法利用形成邻近栅极叠层的具有减小的高度“切口”的L形间隔物。 优选地，通过沉积两层绝缘材料来形成L形间隔件，在其上形成第三间隔件作为掩模，以去除第一和第二绝缘层的不期望的部分。 通过L形间隔件执行非晶化和深度注入，其中响应于L形间隔件的几何形状，连接轮廓被成型，使得可以利用单个深度注入步骤。 轮廓结中的凹槽可以减少短沟道效应，同时允许硅化物的形成深度超过浇注在栅电极下方的结深度。

公开(公告)号：US06506638B1

公开(公告)日：2003-01-14

申请号：US09689063

申请日：2000-10-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bonding technique can be utilized to form the substrate.

Abstract translation: 一种垂直晶体管的制造方法。 垂直晶体管利用沉积的非晶硅层形成源区。 垂直栅极晶体管包括用于提供增加的驱动电流的双栅极结构。 可以利用晶片接合技术来形成衬底。

公开(公告)号：US06495402B1

公开(公告)日：2002-12-17

申请号：US09777637

申请日：2001-02-06

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L2100

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer, the active layer having an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween, each of the source and the drain having a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon, the silicon-germanium regions forming heterojunction portions respectively along the source/body junction and the drain/body junction. A method of fabricating the SOI device is also disclosed.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层，该有源层具有由隔离区域限定的有源区域，该有源区域具有源极和漏极，其间设置有一个主体 源极和漏极中的每一个具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层之下，硅 - 锗区域分别沿着源极/主体结和漏极/本体结形成异质结部分。 还公开了制造SOI器件的方法。

公开(公告)号：US06482705B1

公开(公告)日：2002-11-19

申请号：US09825659

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/665

Abstract: A method of fabricating a semiconductor device, having a MOSFET with an amorphous-silicon-germanium gate electrode and an elevated crystalline silicon-germanium source/drain structure for preventing adverse reaction with an underlying silicon substrate, and a device thereby formed. The gate electrode and the raised S/D structure are simultaneously formed by depositing and polishing an amorphous-silicon-germanium film and subsequently heating the polished an amorphous-silicon-germanium film in a low temperature range. Generally, the method involves: (1) depositing an amorphous-silicon-germanium layer; (2) simultaneously forming a raised source/drain structure and a gate electrode by polishing the amorphous-silicon-germanium layer; and (3) annealing the raised source/drain structure and a gate electrode.

Abstract translation: 一种制造半导体器件的方法，其具有具有非晶硅锗锗栅极的MOSFET和用于防止与下面的硅衬底的不利反应的升高的晶体硅 - 锗源极/漏极结构以及由此形成的器件。 通过沉积和抛光非晶硅 - 锗膜并随后在低温范围内加热抛光的非晶硅 - 锗膜，同时形成栅电极和升高的S / D结构。 通常，该方法包括：（1）沉积非晶硅 - 锗层; （2）通过抛光非晶硅 - 锗层同时形成升高的源/漏结构和栅电极; 和（3）对升高的源极/漏极结构和栅电极进行退火。

公开(公告)号：US06468888B1

公开(公告)日：2002-10-22

申请号：US09685974

申请日：2000-10-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/4966 ,  H01L21/2807 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823828

Abstract: A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在衬底上形成晶体管栅极和由此制成的半导体器件。 栅极通过在衬底上沉积多晶硅层，以比较低的剂量将锗注入到多晶硅层中，然后氧化掺杂的多晶硅层而形成。 在氧化的影响下，锗从多晶硅层的上部牺牲区域排斥到多晶硅层的下部栅极区域，从而增加下部栅极区域中的锗浓度。 然后蚀刻掉牺牲区域，并且在栅极区域上沉积未掺杂的多晶硅膜。 随后，对具有未掺杂多晶硅膜的栅极区域进行构图以建立MOSFET栅极，然后适当地处理衬底以建立MOSFET源极/漏极区域。

公开(公告)号：US06458662B1

公开(公告)日：2002-10-01

申请号：US09826551

申请日：2001-04-04

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/78687 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, involving: patterning a silicon-on-insulator (SOI) wafer with a photoreist layer, wherein the SOI structure comprises a silicon dioxide (SiO2) layer, a silicon (Si) layer deposited on the SiO2 layer, and a silicon nitride (Si3N4) layer deposited on the Si layer; initiating formation of a SiGe/Si/SiGe sandwich fin structure from the SOI structure; completing formation of the SiGe/Si/SiGe sandwich fin structure; depositing a thick gate material layer on the SiGe/Si/SiGe sandwich fin structure; forming an asymmetrical dual-gate; and completing fabrication of the semiconductor device, and a device thereby formed.

Abstract translation: 一种制造具有硅 - 锗（SiGe）沟道的非对称双栅极MOSFET的半导体器件的方法，包括：利用光刻层构图绝缘体上硅（SOI）晶片，其中SOI结构包括硅 二氧化硅（SiO 2）层，沉积在SiO 2层上的硅（Si）层和沉积在Si层上的氮化硅（Si 3 N 4）层; 从SOI结构开始形成SiGe / Si / SiGe夹层结构; 完成SiGe / Si / SiGe夹层结构的形成; 在SiGe / Si / SiGe夹层结构上沉积厚栅极材料层; 形成不对称双门; 并完成半导体器件的制造，以及由此形成的器件。

公开(公告)号：US06451656B1

公开(公告)日：2002-09-17

申请号：US09796283

申请日：2001-02-28

Applicant: Bin Yu ,  William G. En

Inventor： Bin Yu ,  William G. En

IPC: H01L21336

CPC classification number: H01L29/66742 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer.

Abstract translation: 一种从绝缘体上半导体（SOI）晶片形成半导体线的方法，SOI晶片具有设置在其上的掩埋氧化物（BOX）层的基板和设置在BOX层上的半导体有源层。 该方法包括以下步骤：（a）在有源层上形成虚拟岛; （b）形成靠近所述假岛的侧壁间隔物; （c）去除虚岛; （d）去除由侧壁间隔物露出的有源层的半导体材料; 和（e）去除侧壁间隔物。

公开(公告)号：US06423647B1

公开(公告)日：2002-07-23

申请号：US09734291

申请日：2000-12-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2131

CPC classification number: H01L21/823462 ,  H01L21/31662

Abstract: For fabricating regions of dielectric material on a semiconductor substrate, a first layer of metal is deposited on the semiconductor substrate, and a first opening is etched through the first layer of metal at a first location area on the semiconductor substrate. First laser beams having a first laser power are directed toward the semiconductor substrate to form a first region of dielectric material having a first thickness at the first location area on the semiconductor substrate. The first layer of metal reflects the first laser beams away from the semiconductor substrate except at the first location area, and the first thickness of the first region of dielectric material is determined by the first laser power of the first laser beams. The first layer of metal is removed from the semiconductor substrate. A second layer of metal is then deposited on the semiconductor substrate, and a second opening is etched through the second layer of metal at a second location area on the semiconductor substrate. Second laser beams having a second laser power is directed toward the semiconductor substrate to form a second region of dielectric material having a second thickness at the second location area on the semiconductor substrate. The second layer of metal reflects the second laser beams away from the semiconductor substrate except at the second location area, and the second thickness of the second region of dielectric material is determined by the second laser power of the second laser beams. The second layer of metal is then removed from the semiconductor substrate. The present invention may be used to particular advantage when the first thickness of the first region of dielectric material is different from the second thickness of the second region of dielectric material.

Abstract translation: 为了在半导体衬底上制造介电材料区域，在半导体衬底上沉积第一金属层，并且在半导体衬底上的第一位置区域，通过第一金属层蚀刻第一开口。 具有第一激光功率的第一激光束被引向半导体衬底，以在半导体衬底上的第一位置区域形成具有第一厚度的介电材料的第一区域。 第一金属层将第一激光束反射离开第一位置区域之外的半导体衬底，并且第一区域的第一厚度由第一激光束的第一激光功率决定。 从半导体衬底去除第一金属层。 然后在半导体衬底上沉积第二层金属，并且在半导体衬底上的第二位置区域，通过第二金属层蚀刻第二开口。 具有第二激光功率的第二激光束指向半导体衬底，以在半导体衬底上的第二位置区域形成具有第二厚度的介电材料的第二区域。 第二层金属将第二激光束反射离开第二位置区域以外的半导体衬底，并且第二区域的第二厚度由第二激光束的第二激光功率决定。 然后从半导体衬底去除第二层金属。 当电介质材料的第一区域的第一厚度不同于介电材料的第二区域的第二厚度时，本发明可被用于特别有利。

公开(公告)号：US06423599B1

公开(公告)日：2002-07-23

申请号：US09846793

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: For fabricating a field effect transistor having dual gates, on a buried insulating layer in SOI (semiconductor on insulator) technology, a first layer of first semiconductor material is deposited on the buried insulating material. The first layer of first semiconductor material is patterned to form a first semiconductor island having a first top surface and a second semiconductor island having a second top surface. The first and second semiconductor islands are comprised of the first semiconductor material. An insulating material is deposited to surround the first and second semiconductor islands, and the insulating material is polished down until the first and second top surfaces of the first and second semiconductor islands are exposed such that sidewalls of the first and second semiconductor islands are surrounded by the insulating material. A gate dopant is implanted into the second semiconductor island. A layer of back gate dielectric material is deposited on the first and second top surfaces of the first and second semiconductor islands. An opening is patterned through the layer of back gate dielectric material above the first semiconductor island such that a bottom wall of the opening is formed by the first top surface of the first semiconductor island. A second layer of second semiconductor material is grown from the exposed first top surface of the first semiconductor island and onto the layer of back gate dielectric material. A front gate dielectric is formed over a portion of the second layer of second semiconductor material disposed over the second semiconductor island. A front gate electrode is formed over the front gate dielectric. The second semiconductor island forms a back gate electrode, and a portion of the layer of back gate dielectric material under the front gate dielectric forms a back gate dielectric.

Abstract translation: 为了制造具有双栅极的场效应晶体管，在SOI（绝缘体上半导体）技术的掩埋绝缘层上，第一半导体材料层沉积在掩埋绝缘材料上。 第一层第一半导体材料被图案化以形成具有第一顶表面的第一半导体岛和具有第二顶表面的第二半岛。 第一和第二半导体岛由第一半导体材料组成。 沉积绝缘材料以包围第一和第二半导体岛，并且绝缘材料被抛光直到第一和第二半导体岛的第一和第二顶表面被暴露，使得第一和第二半导体岛的侧壁被 绝缘材料。 将栅极掺杂剂注入第二半导体岛。 一层背栅介质材料沉积在第一和第二半导体岛的第一和第二顶表面上。 通过第一半导体岛上方的背栅介质材料层图案化开口，使得开口的底壁由第一半导体岛的第一顶表面形成。 第二层第二半导体材料从第一半导体岛的暴露的第一顶表面生长到背栅电介质材料层上。 在位于第二半导体岛上的第二半导体材料的第二层的一部分上形成前栅极电介质。 前栅电极形成在前栅极电介质上。 第二半导体岛形成背栅电极，并且在前栅极电介质下方的背栅介质材料层的一部分形成背栅电介质。

公开(公告)号：US06420767B1

公开(公告)日：2002-07-16

申请号：US09605920

申请日：2000-06-28

Applicant: Srinath Krishnan ,  John C. Holst ,  Bin Yu

Inventor： Srinath Krishnan ,  John C. Holst ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/78621 ,  H01L29/7841 ,  H01L29/78612

Abstract: A transistor structure is provided comprising a source region having a N+ source region and a N− lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N− lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N− lightly doped source region and N− lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.

Abstract translation: 提供一种晶体管结构，其包括具有N +源极区域和N-轻掺杂源极区域的源极区域。 该结构还包括具有N +漏极区域和N-轻掺杂漏极区域的漏极区域。 提供了P ++重掺杂区域。 P ++区域与N-轻掺杂源区域和N-轻掺杂漏极区域中的至少一个的至少一部分一起存在。 P +体区域位于器件的栅极之下以及源极和漏极区域之间。 P +⇄重掺杂区域在器件区域和器件的栅极之间提供电容耦合，并与器件的结电容形成电容分压器。