公开(公告)号：US06451656B1

公开(公告)日：2002-09-17

申请号：US09796283

申请日：2001-02-28

Applicant: Bin Yu ,  William G. En

Inventor： Bin Yu ,  William G. En

IPC: H01L21336

CPC classification number: H01L29/66742 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer.

Abstract translation: 一种从绝缘体上半导体（SOI）晶片形成半导体线的方法，SOI晶片具有设置在其上的掩埋氧化物（BOX）层的基板和设置在BOX层上的半导体有源层。 该方法包括以下步骤：（a）在有源层上形成虚拟岛; （b）形成靠近所述假岛的侧壁间隔物; （c）去除虚岛; （d）去除由侧壁间隔物露出的有源层的半导体材料; 和（e）去除侧壁间隔物。

公开(公告)号：US06448114B1

公开(公告)日：2002-09-10

申请号：US10128831

申请日：2002-04-23

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L218234

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.

Abstract translation: 一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。 该方法还包括在第一和第二瓦片较厚的区域中从有源层形成多个部分耗尽的半导体器件，并且在较薄的区域中从有源层形成多个完全耗尽的半导体器件 第一和第二个瓷砖。

公开(公告)号：US06414355B1

公开(公告)日：2002-07-02

申请号：US09770708

申请日：2001-01-26

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L2701

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.

Abstract translation: 绝缘体上硅（SOI）芯片。 SOI芯片具有基板; 设置在基板上的掩埋氧化物（BOX）层; 以及设置在所述BOX层上的有源层，所述有源层被分为第一和第二瓦片，所述第一瓦片具有第一厚度，所述第二瓦片具有第二厚度，所述第二厚度小于所述第一厚度。 还公开了一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。

公开(公告)号：US06765227B1

公开(公告)日：2004-07-20

申请号：US10116791

申请日：2002-04-04

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2906

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract translation: 绝缘体上半导体（SOI）晶片。 晶片包括硅衬底，设置在衬底上的掩埋氧化物（BOX）层和设置在盒层上的有源层。 有源层具有设置在硅 - 锗层上的上硅层。 硅 - 锗层设置在下硅层上。 硅 - 锗层的硅 - 锗是应变的硅 - 锗，并且是大约至大约400埃。

公开(公告)号：US06566213B2

公开(公告)日：2003-05-20

申请号：US09824123

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L21/823443 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66772 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的一次性间隔件。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

公开(公告)号：US06410371B1

公开(公告)日：2002-06-25

申请号：US09794884

申请日：2001-02-26

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2184

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

Abstract translation: 一种形成绝缘体上半导体（SOI）晶片的方法。 该方法包括提供第一晶片，第一晶片具有硅衬底和设置在其上的氧化物层的步骤; 提供第二晶片，所述第二晶片具有硅衬底，所述第二晶片的衬底具有设置在其上的硅 - 锗层，设置在所述硅 - 锗层上的硅层和设置在所述硅层上的氧化物层; 晶片接合第一和第二晶片; 以及从所述第二晶片去除所述衬底的不希望的部分以形成上硅层。 还公开了所得到的SOI晶片结构。

公开(公告)号：US06441433B1

公开(公告)日：2002-08-27

申请号：US09824412

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L3113

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，器件包括形成在主源极和漏极区域以及源极和漏极延伸区域上的多层硅化物层，其中形成在源极和漏极延伸区域上的多层硅化物层的一部分比部分 形成在主源极和漏极区上的硅化物层。 该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。

公开(公告)号：US06518631B1

公开(公告)日：2003-02-11

申请号：US09824418

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L31113

CPC classification number: H01L29/6653 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的多个间隔物。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

公开(公告)号：US20150286441A1

公开(公告)日：2015-10-08

申请号：US14746582

申请日：2015-06-22

Applicant: Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

Inventor： Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

IPC: G06F3/06

CPC classification number: H04L41/0659 ,  G06F11/006 ,  G06F11/0709 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1423 ,  G06F17/30194 ,  H04L67/06 ,  H04L67/1097

Abstract: A method and a system to provide daisy chain distribution in data centers are provided. A node identification module identifies three or more data nodes of a plurality of data nodes. The identification of three or more data nodes indicates that the respective data nodes are to receive a copy of a data file. A connection creation module to, using one or more processors, create communication connections between the three or more data nodes. The communication connections form a daisy chain beginning at a seeder data node of the three or more data nodes and ending at a terminal data node of the three or more data nodes.

Abstract translation: 提供了一种在数据中心提供菊花链分发的方法和系统。 节点识别模块识别多个数据节点中的三个或多个数据节点。 三个或更多个数据节点的标识指示相应的数据节点要接收数据文件的副本。 连接创建模块，用于使用一个或多个处理器在三个或更多个数据节点之间建立通信连接。 通信连接形成从三个或更多个数据节点的播种器数据节点开始并且结束于三个或更多个数据节点的终端数据节点的菊花链。

公开(公告)号：US09143297B2

公开(公告)日：2015-09-22

申请号：US13977907

申请日：2011-07-21

Applicant: Chunli Liang ,  Bo Dai ,  Bin Yu ,  Weiwei Yang ,  Yuqiang Zhang

Inventor： Chunli Liang ,  Bo Dai ,  Bin Yu ,  Weiwei Yang ,  Yuqiang Zhang

IPC: H04W4/00 ,  H04L5/00

CPC classification number: H04L5/0048 ,  H04L5/0053

Abstract: The present disclosure discloses a method and a device for transmitting data. The method includes: a UE determining, according to a preset rule, whether to transmit PUCCH and/or PUSCH and/or an SRS or not on a last symbol of a current subframe; the UE determining the PUCCH and/or the PUSCH to be transmitted on the current subframe according to availability of the last symbol of the current subframe for transmitting the PUCCH and/or the PUSCH; and the UE transmitting the PUCCH and/or the PUSCH on the current subframe and/or transmitting the SRS on the last symbol of the current subframe. In virtue of the present disclosure, it can be realized that a plurality of types of physical uplink signals/channels are simultaneously transmitted.

Abstract translation: 本公开公开了一种用于发送数据的方法和装置。 该方法包括：UE根据预设规则确定是否在当前子帧的最后一个符号上发送PUCCH和/或PUSCH和/或SRS; UE根据用于发送PUCCH和/或PUSCH的当前子帧的最后一个符号的可用性来确定要在当前子帧上发送的PUCCH和/或PUSCH; 并且UE在当前子帧上发送PUCCH和/或PUSCH，和/或在当前子帧的最后一个符号上发送SRS。 凭借本公开，可以实现同时发送多种类型的物理上行链路信号/信道。