公开(公告)号：US20250008106A1

公开(公告)日：2025-01-02

申请号：US18828169

申请日：2024-09-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/13 ,  H04N19/12 ,  H04N19/167 ,  H04N19/176 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In residual coding of a current block, the circuitry, in operation, encodes a subblock flag by Context-based Adaptive Binary Arithmetic Coding (CABAC) in both of a first type of residual coding where an orthogonal transform is performed and a second type of residual coding where the orthogonal transform is skipped, the subblock flag indicating whether a non-zero coefficient is included in a plurality of coefficients for a subblock within the current block, wherein a first syntax used for the first type of residual coding is different from a second syntax used for the second type of residual coding; and controls a number of CABAC processes, wherein the encoding of the subblock flag is not counted as the number of CABAC processes.

公开(公告)号：US20240422343A1

公开(公告)日：2024-12-19

申请号：US18817774

申请日：2024-08-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Ru Ling LIAO ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/513 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176

Abstract: Provided is an encoder including circuitry and memory coupled to the circuitry. A prediction mode for a current block is an affine mode, and in operation, the circuitry: derives a base motion vector which is a motion vector to be used in a prediction process for the current block, and is a motion vector at an affine-mode control point in the current block; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; if so, modifies a second motion vector different from the base motion vector and the first motion vector, and if not, does not modify the second motion vector; and encodes the current block using the second motion vector modified or the second motion vector not modified.

公开(公告)号：US20240364937A1

公开(公告)日：2024-10-31

申请号：US18758760

申请日：2024-06-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato OHKAWA ,  Hideo SAITOU ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/80 ,  H04N19/176 ,  H04N19/86

CPC classification number: H04N19/80 ,  H04N19/176 ,  H04N19/86

Abstract: For a location displaced by four samples in a vertical direction or a horizontal direction from a current location, the encoder performs a first determination of determining only whether the location displaced by four samples is a TU boundary, where the current location is a sample location of a current sub-block boundary on which the determination process is to be performed. In the first determination, when it is determined that the location displaced by four samples is a TU boundary, the encoder sets a maximum filter length to a first value, and in the case otherwise, the encoder performs a second determination of determining whether a location displaced by eight samples in the vertical direction or the horizontal direction from the current location is a TU boundary.

公开(公告)号：US20240314321A1

公开(公告)日：2024-09-19

申请号：US18673719

申请日：2024-05-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/18 ,  H04N19/46 ,  H04N19/60

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/18 ,  H04N19/46 ,  H04N19/60

Abstract: An encoder including circuitry and memory coupled to the circuitry. In both of a first case where an orthogonal transform is performed and a second case where the orthogonal transform is skipped, when a number of CABAC processes is within an allowable range, the circuitry: encodes a plurality of coefficient information flags by CABAC; and encodes a remainder value of the coefficient; and when the number of CABAC processes is not within the allowable range, the circuitry: skips the encoding of the plurality of coefficient information flags, wherein in the first case, the circuitry: converts the coefficient to a second coefficient by using a poszero value that is determined using a plurality of surrounding coefficients; and encodes a value of the second coefficient, and wherein in the second case, the circuitry: encodes the value of the coefficient.

公开(公告)号：US20240292035A1

公开(公告)日：2024-08-29

申请号：US18649342

申请日：2024-04-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Takahiro NISHI ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/70 ,  H04N19/172 ,  H04N19/174

CPC classification number: H04N19/70 ,  H04N19/172 ,  H04N19/174

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: assigns a picture level slice index and a subpicture level slice index to each of the slices, the picture level slice index being assigned at a picture level, the subpicture level slice index being assigned at a subpicture level; for each of the slices, encodes the subpicture level slice index of the slice into a slice header of the slice; and encodes each of the slices into a bitstream. The picture level slice index assigned to a current slice to be processed that is 10 included in a current subpicture to be processed is calculated by adding (i) the subpicture level slice index of the current slice and (ii) a total number of slices included in one or more subpictures that have been encoded prior to the current subpicture out of the subpictures.

公开(公告)号：US20240291970A1

公开(公告)日：2024-08-29

申请号：US18656952

申请日：2024-05-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon LIM ,  Jing Ya LI ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Yusuke KATO ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Takahiro NISHI

IPC: H04N19/107 ,  H04N19/176

CPC classification number: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US20240195976A1

公开(公告)日：2024-06-13

申请号：US18587635

申请日：2024-02-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/13 ,  H04N19/169 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/1887

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US20240137514A1

公开(公告)日：2024-04-25

申请号：US18403086

申请日：2024-01-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied and a second type of residual coding where the orthogonal transform is skipped, wherein when a restriction on a number of CABAC processes allows CABAC coding of a set of coefficient information flags, the circuitry: encodes the coefficient information flags by CABAC; and otherwise, the circuitry: skips the CABAC encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and otherwise the circuitry encodes a value of the coefficient with the Golomb-Rice code, wherein in the second type of residual coding, the circuitry encodes absolute value flags each relating to an absolute value of the coefficient after encoding the coefficient information flags and before encoding the remainder value of the coefficient.

公开(公告)号：US20240114169A1

公开(公告)日：2024-04-04

申请号：US18526683

申请日：2023-12-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Che Wei KUO ,  Chong Soon LIM ,  Chu Tong WANG ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176

CPC classification number: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US20240064330A1

公开(公告)日：2024-02-22

申请号：US18385469

申请日：2023-10-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/587 ,  H04N19/172 ,  H04N19/132 ,  H04N19/136 ,  H04N19/105 ,  H04N19/503 ,  H04N19/109 ,  H04N19/184 ,  H04N19/463

CPC classification number: H04N19/587 ,  H04N19/172 ,  H04N19/132 ,  H04N19/136 ,  H04N19/105 ,  H04N19/503 ,  H04N19/109 ,  H04N19/184 ,  H04N19/463

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. In operation, the circuitry: controls whether to change a resolution of a picture from a resolution of a previous picture preceding the picture in one of display order and encoding order, according to a constraint that allows the changing only when the picture is a random access picture among one or more random access pictures; and when a resolution of a reference picture to be used in encoding of an inter-predicted picture is different from a resolution of the inter-predicted picture, resamples a reference image in the reference picture according to a difference between the resolution of the reference picture and the resolution of the inter-predicted picture, and encodes an image in the inter-predicted picture using the reference image resampled.