ELECTROSPRAY AND NANOSPRAY IONIZATION OF DISCRETE SAMPLES IN DROPLET FORMAT
    81.
    发明申请
    ELECTROSPRAY AND NANOSPRAY IONIZATION OF DISCRETE SAMPLES IN DROPLET FORMAT 有权
    滴定法中离散样品的电泳和纳米沉淀离子化

    公开(公告)号:US20120153143A1

    公开(公告)日:2012-06-21

    申请号:US13378858

    申请日:2010-06-18

    IPC分类号: H01J49/26 H01J49/10 H01J27/02

    CPC分类号: H01J49/165 B01L3/502784

    摘要: Droplets or plugs within multiphase microfluidic systems have rapidly gained interest as a way to manipulate samples and chemical reactions on the femtoliter to microliter scale. Chemical analysis of the plugs remains a challenge. It has been discovered that nanoliter plugs of sample separated by air or oil can be analyzed by electrospray ionization mass spectrometry when pumped directly into a fused silica nanospray emitter nozzle. Using leu-enkephalin in methanol and 1% acetic acid in water (50:50 v:v) as a model sample, we found carry-over between plugs was

    摘要翻译: 在多相微流体系统中的液滴或塞子已经迅速获得兴趣,作为将飞蓟素的样品和化学反应操纵到微量级的方法。 插头的化学分析仍然是一个挑战。 已经发现,当直接泵送到熔融石英纳米喷雾发射器喷嘴中时,可以通过电喷雾离子化质谱法分析由空气或油分离的样品的纳升塞塞。 在甲醇和1%乙酸水溶液(50:50 v:v)中使用左脑啡肽作为模型样品,发现栓塞之间的滞留量<0.1%,一系列塞子的信号相对标准偏差为3 %。 检测限为1nM。 样品分析速率为0.8 Hz,通过泵送13 mm的样品,通过在内径为75μm的管内3mm长的气隙中分离出来。 分析速率受到离子阱质谱仪扫描时间的限制。 该系统为分段流量系统中样品的化学分析提供了强大,快速和信息丰富的方法。

    Synchronization Method and Device
    82.
    发明申请
    Synchronization Method and Device 有权
    同步方法和设备

    公开(公告)号:US20120099608A1

    公开(公告)日:2012-04-26

    申请号:US13257920

    申请日:2010-03-25

    IPC分类号: H04J3/06

    CPC分类号: H04L27/2656 H04L27/2675

    摘要: A synchronization method is disclosed, including: obtaining a synchronization symbol position {circumflex over (d)}0 of one time slot of an initial update period; taking Ntrack frames as an update period to adjust the synchronization symbol position, and the step of adjusting the synchronization symbol position including: obtaining a synchronization symbol position {circumflex over ({circumflex over (d)}k+1=dk+Ntrack{circumflex over (T)}k of a corresponding time slot of a (k+1)th update period according to a synchronization symbol position {circumflex over (d)}k of a corresponding time slot of a kth update period and an inter-frame sampling derivation estimation value {circumflex over (T)}k of said kth update period; obtaining synchronization symbol positions of other time slots in said kth update period according to the synchronization symbol position {circumflex over (d)}k of the corresponding time slot of the kth update period and the inter-frame sampling derivation estimation value {circumflex over (T)}k of said kth update period. A synchronization apparatus is also disclosed. The method and apparatus reduces synchronization calculation amount.

    摘要翻译: 公开了一种同步方法,其包括:获得初始更新周期的一个时隙的同步符号位置{(d)} 0; 将Ntrack帧作为更新周期来调整同步符号位置,以及调整同步符号位置的步骤包括:获得同步符号位置{circumflex over({circumflex over(d)} k + 1 = dk + Ntrack {circumflex 根据第k个更新周期的对应时隙的同步符号位置{(d)} k的第(k + 1)个更新周期的相应时隙,超过(T)} k个k 根据所述第k个更新周期的采样导出估计值{(f)(k)),根据相应时隙的同步符号位置{(d)} k获得所述第k个更新周期中的其他时隙的同步符号位置 以及所述第k个更新周期的帧间采样导出估计值(在(T)} k的转换,同时还公开了同步装置,该方法和装置减少了同步计算 nt。

    Method and Apparatus for Service Configuration and Rate Matching of Time Division-Synchronous Code Division Multiple Access System
    85.
    发明申请
    Method and Apparatus for Service Configuration and Rate Matching of Time Division-Synchronous Code Division Multiple Access System 有权
    时分同步码分多址系统的业务配置与速率匹配方法与装置

    公开(公告)号:US20120082053A1

    公开(公告)日:2012-04-05

    申请号:US13258079

    申请日:2010-03-31

    IPC分类号: H04W28/04

    CPC分类号: H04L1/0068 H04L1/0052

    摘要: A method for configuring a service and a method and apparatus for rate matching in a TD-SCDMA system, this method for configuring the service includes: taking that a check bit puncturing ratio should be more than 7i+a or less than 7i−a as a newly added constraint condition, and the check bit puncturing ratios of each configured service being outside a range of [7i+a, 7i−a], the method for rate matching includes: when puncturing each path of check bits of the current data block, if a difference between a position Pk of kth reserved check bit calculated according to a method defined by the service and a previously determined position NPk-1 of k−1th reserved check bit is a positive integral multiple of 7, determining a position NPk of kth reserved check bit as Pk plus 1 or Pk minus 1, and Pk plus 1 and Pk minus 1 requiring carrying out alternately.

    摘要翻译: 一种用于配置服务的方法以及用于TD-SCDMA系统中的速率匹配的方法和装置,所述用于配置服务的方法包括:将校验位打孔比应大于7i + a或小于7i-a作为 新添加的约束条件,并且每个配置的服务的检查比特删截比率在[7i + a,7i-a]的范围之外,用于速率匹配的方法包括:当对当前数据块的校验位的每个路径 如果根据由服务定义的方法计算的第k个保留校验位的位置Pk与第k-1个保留校验位的预先确定的位置NPk-1之间的差是7的正整数倍,则确定位置NPk 第k个保留校验位为Pk加1或Pk减1,Pk加1和Pk减1需要交替执行。

    Method and system for calibrating a plurality of modules in a communication system
    86.
    发明授权
    Method and system for calibrating a plurality of modules in a communication system 有权
    用于在通信系统中校准多个模块的方法和系统

    公开(公告)号:US08102953B2

    公开(公告)日:2012-01-24

    申请号:US11618721

    申请日:2006-12-29

    IPC分类号: H04L27/08 H04B1/18

    摘要: A method and system for calibrating a plurality of modules in a communication system is provided. The method may include selecting a plurality of modules with at least one output signal and calibrating an amplitude of each selected module to be within a specified range if the amplitude is out of the specified range via a gain control processing circuit of the selected module, wherein the plurality of modules may be calibrated in an order starting with a first module located at an input of a signal path and ending with a module located at an output of the signal path. The DC component and amplitude of the envelope of the output signal may be detected by circuitry within the selected module. Muxes may be utilized to route the DC component and amplitude of the envelope to a feedback control processing circuit.

    摘要翻译: 提供了一种用于在通信系统中校准多个模块的方法和系统。 该方法可以包括:通过所选择的模块的增益控制处理电路,如果振幅超出指定范围,则选择具有至少一个输出信号的多个模块,并将每个所选模块的振幅校准在指定范围内,其中 多个模块可以以从位于信号路径的输入端的第一模块开始并以位于信号路径的输出端的模块结束的顺序被校准。 输出信号的包络的直流分量和振幅可由所选模块内的电路检测。 可以利用复用器将DC分量和信号的幅度路由到反馈控制处理电路。

    ON-CHIP CAPACITOR STRUCTURE
    87.
    发明申请
    ON-CHIP CAPACITOR STRUCTURE 有权
    片上电容结构

    公开(公告)号:US20120007215A1

    公开(公告)日:2012-01-12

    申请号:US13236536

    申请日:2011-09-19

    IPC分类号: H01L27/06

    摘要: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

    摘要翻译: 至少第一电容器形成在衬底上并连接到差分电路的第一差分节点,并且第一电容器可以是可变电容的。 第二电容器形成在衬底上并连接到差分电路的第二差分节点,并且第二电容器也可以是可变的。 第三电容器连接在第一差分节点和第二差分节点之间,并且至少部分地形成在第一电容器的上方。 以这种方式,可以在衬底上减小第一电容器和/或第二电容器的尺寸,并且可以响应于一个或多个电路的可变特性来调整第一和/或第二电容器的电容 差分电路的组件。

    Configurable Clock Signal Generator
    88.
    发明申请
    Configurable Clock Signal Generator 有权
    可配置时钟信号发生器

    公开(公告)号:US20110018604A1

    公开(公告)日:2011-01-27

    申请号:US12539495

    申请日:2009-08-11

    IPC分类号: H03L5/00

    CPC分类号: H03L1/00 H03B5/368

    摘要: A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.

    摘要翻译: 本文描述了提供低功率时钟信号或低噪声时钟信号的方法。 确定是否使用低功率模式或低噪声模式。 低压差稳压器(LDO)的参考电压输入端被切换到低功耗模式的低功耗参考电压,低噪声模式的低噪声电压基准用。 LDO为晶体振荡器提供恒定电压输出。 使用晶体振荡器产生时钟信号。 使用低功率限幅器来限制时钟信号以产生低功率输出时钟信号和/或使用低噪声限制器来限制以产生低噪声时钟信号。 使用多路复用器选择低功耗输出时钟信号或低噪声输出时钟信号。

    Method and system of generating a point-in-time image of at least a portion of a database
    89.
    发明授权
    Method and system of generating a point-in-time image of at least a portion of a database 有权
    生成数据库的至少一部分的时间点图像的方法和系统

    公开(公告)号:US07831564B1

    公开(公告)日:2010-11-09

    申请号:US10737281

    申请日:2003-12-16

    IPC分类号: G06F7/00 G06F17/00

    CPC分类号: G06F11/1458 G06F11/1469

    摘要: A method and system of generating a point-in-time image of at least a portion of a database is disclosed. According to one embodiment, a method is provided wherein a plurality of components of a database are discovered, a component of the plurality of components is selected, a data management resource of a plurality of data management resources is selected using an attribute of the component, and a point-in-time image of the component is generated using the data management resource.

    摘要翻译: 公开了一种生成数据库的至少一部分的时间点图像的方法和系统。 根据一个实施例,提供了一种方法,其中发现数据库的多个组件,选择多个组件的组件,使用组件的属性来选择多个数据管理资源的数据管理资源, 并且使用数据管理资源生成组件的时间点图像。