公开(公告)号：US07879727B2

公开(公告)日：2011-02-01

申请号：US12354480

申请日：2009-01-15

申请人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

发明人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

IPC分类号： H01L21/311

CPC分类号： H01L27/11 ,  G03F7/40 ,  G03F7/7035 ,  H01L21/32139

摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.

摘要翻译： 一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在 抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有 初始宽度。 该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分 硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

公开(公告)号：US20100163995A1

公开(公告)日：2010-07-01

申请号：US12720700

申请日：2010-03-10

申请人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

发明人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L23/367 ,  H01L27/0248 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed

摘要翻译： 本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态 靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。 还公开了其他实施例

公开(公告)号：US20100129968A1

公开(公告)日：2010-05-27

申请号：US12622075

申请日：2009-11-19

申请人： Hong-Jyh Li ,  Thomas Schulz

发明人： Hong-Jyh Li ,  Thomas Schulz

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645

摘要： Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

摘要翻译： 公开了具有不同栅介电材料的晶体管的半导体器件及其制造方法。 一个实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一晶体管设置在工件的第一区域中，第一晶体管具有至少两个第一栅电极。 第一栅极电介质设置在所述至少两个第一栅电极中的每一个附近，所述第一栅极电介质包括第一材料。 第二晶体管设置在工件的第二区域中，第二晶体管具有至少两个第二栅电极。 第二栅极电介质设置在所述至少两个第二栅电极中的每一个附近，所述第二栅极电介质包括第二材料。 第二种材料与第一种材料不同。

公开(公告)号：US07646046B2

公开(公告)日：2010-01-12

申请号：US11559656

申请日：2006-11-14

申请人： Christian Russ ,  Harald Gossner ,  Thomas Schulz

发明人： Christian Russ ,  Harald Gossner ,  Thomas Schulz

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78621

摘要： A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.

摘要翻译： 一种具有鳍结构的场效应晶体管，具有第一和第二源极/漏极区域; 形成在所述鳍结构内并且在所述第一和第二源极/漏极区之间的体区; 形成在所述第一源极/漏极区域的一部分内的金属导电区域，所述金属导电区域邻近所述体区域或者设置在所述体区域和所述第一源极/漏极区域之间的轻掺杂区域; 以及形成在第二源极/漏极区域的一部分内的电流镇流区域。

公开(公告)号：US20090209097A1

公开(公告)日：2009-08-20

申请号：US12032295

申请日：2008-02-15

申请人： Thomas Schulz ,  Sergei Postnikov ,  Hans-Joachim Barth ,  Klaus von Arnim

发明人： Thomas Schulz ,  Sergei Postnikov ,  Hans-Joachim Barth ,  Klaus von Arnim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/31144

摘要： A method of forming interconnects includes etching a first set of openings in a hard mask using a first photo resist layer with a first pattern of openings as a first etch mask, and etching a second set of openings in the hard mask using a second photo resist layer with a second pattern of openings as a second etch mask. The method includes shrinking the openings in at least one of the first pattern and the second pattern prior to etching the openings in the hard mask.

摘要翻译： 一种形成互连的方法包括使用具有第一开口图案的第一光致抗蚀剂层作为第一蚀刻掩模蚀刻在硬掩模中的第一组开口，以及使用第二光致抗蚀剂蚀刻硬掩模中的第二组开口 层，其具有作为第二蚀刻掩模的第二开口图案。 该方法包括在蚀刻硬掩模中的开口之前收缩第一图案和第二图案中的至少一个中的开口。

公开(公告)号：US20090114979A1

公开(公告)日：2009-05-07

申请号：US12349062

申请日：2009-01-06

申请人： Thomas Schulz

发明人： Thomas Schulz

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/78684 ,  H01L29/78687

摘要： A semiconductor device includes a source region, a drain region, and a fin that connects the source region to the drain region. A gate electrode having a substantially planar surface overlies the fin and is positioned between the drain region and the source region. A first set of spacers is positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region. A second set of spacers is positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers. At least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode.

摘要翻译： 半导体器件包括源极区域，漏极区域和将源极区域连接到漏极区域的鳍片。 具有基本上平坦表面的栅极电极覆盖在鳍片之间并且位于漏极区域和源极区域之间。 第一组间隔物定位在栅极电极的第一侧壁和源极区域之间以及栅极电极的第二侧壁和漏极区域之间。 第二组间隔物定位在源区和漏区的顶表面的至少一部分上，并且与第一组间隔物的至少一部分一起。 第二组间隔物的侧壁的至少一部分接触栅电极的第一或第二侧壁的一部分。

公开(公告)号：US20080211025A1

公开(公告)日：2008-09-04

申请号：US12055601

申请日：2008-03-26

申请人： Ralf Gottsche ,  Christian Pacha ,  Thomas Schulz ,  Werner Steinhogl

发明人： Ralf Gottsche ,  Christian Pacha ,  Thomas Schulz ,  Werner Steinhogl

IPC分类号： H01L27/12

CPC分类号： H01L29/78654 ,  H01L21/28123 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78642

摘要： A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.

摘要翻译： 具有预定晶体管特性的第一SOI场效应晶体管，包括：具有栅极绝缘层和未掺杂衬底上的栅极区域的横向限定层序列; 在横向限定的层序列的侧壁的至少一部分上具有预定厚度的间隔层; 以及与所述间隔层相邻的衬底的两个表面区域中的两个源极/漏极区域，具有预定的掺杂剂浓度分布，所述层序列和间隔层形成遮光结构，所述遮蔽结构防止掺杂剂被引入到 在制造第一SOI场效应晶体管期间在两个源极/漏极区之间的衬底，其中通过设置间隔层的厚度和掺杂剂浓度分布来设定第一SOI场效应晶体管的预定晶体管特性。

公开(公告)号：US07265424B2

公开(公告)日：2007-09-04

申请号：US10768971

申请日：2004-01-30

申请人： Franz Hofmann ,  Johannes Kretz ,  Wolfgang Roesner ,  Thomas Schulz

发明人： Franz Hofmann ,  Johannes Kretz ,  Wolfgang Roesner ,  Thomas Schulz

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once the gate has been produced.

摘要翻译： 具有衬底的翅片场效应晶体管，衬底上方的鳍结构，以及衬底上方的鳍状结构之外的漏极区域和源极区域。 鳍结构用作源极区域和漏极区域之间的沟道。 一旦栅极生产就形成源区和漏区。

公开(公告)号：US20070137807A1

公开(公告)日：2007-06-21

申请号：US11300750

申请日：2005-12-15

申请人： Thomas Schulz ,  Malcolm Halls

发明人： Thomas Schulz ,  Malcolm Halls

IPC分类号： D21F11/14

CPC分类号： D21H27/005

摘要： A durable single-ply uncreped paper towel having an increased level of geometric mean total energy absorbed (GMTEA) per geometric mean tensile (GMT) and an increased level of cross-machine direction total energy absorbed (CDTEA) per cross-machine direction tensile strength is disclosed. A method of making such a paper towel is also disclosed.

摘要翻译： 一种耐用的单层未擦拭纸巾，每个几何平均拉伸（GMT）几何平均总吸收能量水平（GMTEA）增加，跨机器方向总吸收能量（CDTEA）每横向拉伸强度增加 被披露。 还公开了制造这种纸巾的方法。

公开(公告)号：US20070075351A1

公开(公告)日：2007-04-05

申请号：US11240698

申请日：2005-09-30

申请人： Thomas Schulz ,  Hongfa Luan

发明人： Thomas Schulz ,  Hongfa Luan

IPC分类号： H01L29/76

CPC分类号： H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

摘要翻译： 公开了半导体器件及其制造方法。 互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数 参数。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。