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公开(公告)号：US07416927B2
公开(公告)日：2008-08-26
申请号：US10948637
申请日：2004-09-23
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78642
摘要： Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.
摘要翻译： 在具有预定晶体管性质的第一SOI场效应晶体管的制造方法中，通过在未掺杂的衬底上形成具有栅极绝缘层和栅极区域的横向限定的层序列，在至少一部分上形成具有预定厚度的间隔层 横向限定的层序列的侧壁，并且通过将掺杂剂引入到由间隔层邻接的衬底的两个表面区域中，形成具有预定掺杂剂浓度分布的两个源极/漏极区域，层序列和间隔层形成 防止掺杂剂被引入到两个源极/漏极区域之间的衬底的表面区域的阴影结构，其中通过设置间隔层的厚度并且通过设置掺杂剂来设定第一SOI场效应晶体管的预定晶体管特性 浓度分布。
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2.发明申请公开(公告)号：US20080211025A1
公开(公告)日：2008-09-04
申请号：US12055601
申请日：2008-03-26
IPC分类号： H01L27/12
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78642
摘要： A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.
摘要翻译： 具有预定晶体管特性的第一SOI场效应晶体管，包括：具有栅极绝缘层和未掺杂衬底上的栅极区域的横向限定层序列; 在横向限定的层序列的侧壁的至少一部分上具有预定厚度的间隔层; 以及与所述间隔层相邻的衬底的两个表面区域中的两个源极/漏极区域，具有预定的掺杂剂浓度分布，所述层序列和间隔层形成遮光结构，所述遮蔽结构防止掺杂剂被引入到 在制造第一SOI场效应晶体管期间在两个源极/漏极区之间的衬底，其中通过设置间隔层的厚度和掺杂剂浓度分布来设定第一SOI场效应晶体管的预定晶体管特性。
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3.发明申请Method for producing an SOI field effect transistor and corresponding field effect transistor 有权用于制造SOI场效应晶体管和相应场效应晶体管的方法公开(公告)号：US20050106789A1
公开(公告)日：2005-05-19
申请号：US10948637
申请日：2004-09-23
IPC分类号： H01L21/28 , H01L21/336 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78642
摘要： Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.
摘要翻译： 在具有预定晶体管性质的第一SOI场效应晶体管的制造方法中，通过在未掺杂的衬底上形成具有栅极绝缘层和栅极区域的横向限定的层序列，在至少一部分上形成具有预定厚度的间隔层 横向限定的层序列的侧壁，并且通过将掺杂剂引入到由间隔层邻接的衬底的两个表面区域中，形成具有预定掺杂剂浓度分布的两个源极/漏极区域，层序列和间隔层形成 防止掺杂剂被引入到两个源极/漏极区域之间的衬底的表面区域的阴影结构，其中通过设置间隔层的厚度并且通过设置掺杂剂来设定第一SOI场效应晶体管的预定晶体管特性 浓度分布。
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4.发明申请SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开半导体电路布置及相关的温度检测方法公开(公告)号：US20110013668A1
公开(公告)日：2011-01-20
申请号：US12888528
申请日：2010-09-23
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译： 公开了半导体电路装置和温度检测方法。 一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。 在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极 实现场效应晶体管。 在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层 边区。
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公开(公告)号：US07820505B2
公开(公告)日：2010-10-26
申请号：US11862640
申请日：2007-09-27
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。
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公开(公告)号：US20080038888A1
公开(公告)日：2008-02-14
申请号：US11862640
申请日：2007-09-27
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。
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7.发明授权Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权具有电容器并具有平面晶体管和制造方法的集成电路装置公开(公告)号：US07173302B2
公开(公告)日：2007-02-06
申请号：US10531493
申请日：2003-10-10
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。
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公开(公告)号：US08124475B2
公开(公告)日：2012-02-28
申请号：US12414120
申请日：2009-03-30
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。
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公开(公告)号：US20090184355A1
公开(公告)日：2009-07-23
申请号：US12414120
申请日：2009-03-30
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。
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10.发明申请Integrated circuit arrangement comprising capacitors and preferably planar transistors, and production method 有权集成电路装置，包括电容器和优选平面晶体管，以及制造方法公开(公告)号：US20060022302A1
公开(公告)日：2006-02-02
申请号：US10531493
申请日：2003-10-10
IPC分类号： H01L29/00
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。
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