公开(公告)号：US09496877B2

公开(公告)日：2016-11-15

申请号：US14346270

申请日：2011-09-30

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: H03K19/20 ,  G11C8/08 ,  G11C11/408

CPC classification number: H03K19/20 ,  G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).

Abstract translation: 本发明涉及一种电路，其包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管 第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作 （G2p，G2N）。

公开(公告)号：US09135964B2

公开(公告)日：2015-09-15

申请号：US13456020

申请日：2012-04-25

Applicant: Richard Ferrant ,  Roland Thewes

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/12 ,  G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

Abstract translation: 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端 位线和具有连接到第二位线（/ BL）的输出的第二CMOS反相器和连接到第一位线的输入。 每个CMOS反相器包括上拉和下拉晶体管，其中上拉晶体管或下拉晶体管中的任一个的源极电耦合并连接到上拉电压源或下拉电压源，而没有 在晶体管的源极和电压源之间的中间晶体管。

公开(公告)号：US08953399B2

公开(公告)日：2015-02-10

申请号：US13456047

申请日：2012-04-25

Applicant: Richard Ferrant ,  Roland Thewes

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091

CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C2207/002

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.

Abstract translation: 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端， 以及具有连接到第二位线的输出和连接到第一位线的输入的第二CMOS反相器。 每个CMOS反相器包括上拉晶体管和下拉晶体管，并且读出放大器具有一对传输栅晶体管，被布置为将第一和第二位线连接到第一和第二全局位线。 有利的是，栅极晶体管由上拉晶体管或下拉晶体管构成。

公开(公告)号：US20140225648A1

公开(公告)日：2014-08-14

申请号：US14346270

申请日：2011-09-30

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: H03K19/20

CPC classification number: H03K19/20 ,  G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).

Abstract translation: 本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管 第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作 （G2p，G2N）。

公开(公告)号：US08652887B2

公开(公告)日：2014-02-18

申请号：US13416813

申请日：2012-03-09

Applicant: Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

Inventor： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/76254 ,  H01L21/02238 ,  H01L21/32 ,  H01L21/84 ,  H01L27/1203

Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.

Abstract translation: 本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。 该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释 通过退火。

公开(公告)号：US08384425B2

公开(公告)日：2013-02-26

申请号：US12961293

申请日：2010-12-06

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: H03K19/173 ,  H03K3/01 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11807

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

Abstract translation: 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中， 源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。 所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟 晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。 本发明还提供了操作这种半导体器件结构的方法。

公开(公告)号：US08304833B2

公开(公告)日：2012-11-06

申请号：US12974822

申请日：2010-12-21

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: H04L27/12

CPC classification number: H01L29/7841 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0711 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/4236 ,  H01L29/66825 ,  H01L29/7302 ,  H01L29/7881

Abstract: The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.

Abstract translation: 本发明提供了形成在绝缘体上半导体（SeOI）衬底上并且包括一个或多个FET晶体管的存储单元的各种实施例。 每个FET晶体管具有源极区和漏极区，其至少部分布置在SeOI衬底的薄层中，其中形成沟槽的沟道区和形成在沟槽中的栅极区。 具体地，源极，漏极和沟道区域还具有也被布置在SeOI衬底的绝缘层下方的部分; 绝缘层下方的沟道区域的部分在绝缘层下方的源极和漏极区的部分之间延伸; 并且沟道区域中的沟槽延伸到基底衬底的深度超过绝缘层。 而且，制造这种存储单元的方法和包括多个这样的存储单元的存储器阵列。

公开(公告)号：US20120275254A1

公开(公告)日：2012-11-01

申请号：US13456057

申请日：2012-04-25

Applicant: Richard Ferrant ,  Roland Thewes

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.

Abstract translation: 本发明涉及用于感测存储在存储单元阵列的多个存储器单元中的数据的差分读出放大器，包括具有连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入 第一位线和第二CMOS反相器，其具有连接到第二位线的输出和连接到第一位线（BL）的输入。 每个CMOS反相器包括一个上拉晶体管和一个下拉晶体管，其中读出放大器具有一对分别耦合到第一和第二位线的预充电晶体管，以将第一和第二位线预充电到预充电 电压。 预充电晶体管由上拉晶体管或下拉晶体管构成。

公开(公告)号：US20120250444A1

公开(公告)日：2012-10-04

申请号：US13495632

申请日：2012-06-13

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C8/08 ,  G05F3/02

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

Abstract translation: 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US20120231606A1

公开(公告)日：2012-09-13

申请号：US13416813

申请日：2012-03-09

Applicant: Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

Inventor： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/02238 ,  H01L21/32 ,  H01L21/84 ,  H01L27/1203

Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.

Abstract translation: 本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。 该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释 通过退火。