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    Direct communication with a processor internal to a memory device
    81.
    发明授权
    Direct communication with a processor internal to a memory device 有权

    公开(公告)号：US09606807B2

    公开(公告)日：2017-03-28

    申请号：US12478450

    申请日：2009-06-04

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G06F9/38 ,  G06F15/78

    CPC classification number: G06F9/3877 ,  G06F15/7821 ,  Y02D10/12 ,  Y02D10/13

    Abstract: Devices, systems, and methods of communicating information directly to a sequencer or a buffer in a memory device are provided. In some embodiments, instructions are sent directly from an external processor to a sequencer in the memory device, and the sequencer configures the instructions for an internal processor, such as one or more arithmetic logic units (ALUs) embedded on the memory device. Further, data to be operated on by the internal processor can be sent directly from the external processor to a buffer, and the sequencer can copy the data from the buffer to the internal processor. As power can be consumed each time a memory array is written to or read from, the direct communication of instructions and/or data can reduce the power consumed in writing to or reading from the memory array.

    MULTI-PORT MEMORY DEVICES AND METHODS
    82.
    发明申请
    MULTI-PORT MEMORY DEVICES AND METHODS 有权
    多端口存储器件和方法

    公开(公告)号：US20120314523A1

    公开(公告)日：2012-12-13

    申请号：US13589844

    申请日：2012-08-20

    Applicant: Robert Walker ,  Dan Skinner

    Inventor： Robert Walker ,  Dan Skinner

    IPC: G11C8/16

    CPC classification number: G06F12/0646 ,  G06F13/1668 ,  G06F2212/1041 ,  G11C7/1075

    Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

    Abstract translation: 多端口存储设备的实施例可以包括多个端口和多个存储器组，其中一些存储器组中的一些是每个端口的本地的，并且其中一些对于每个端口是非本地的。 存储器设备可以包括配置寄存器，其存储指示存储器组到端口的映射的配置数据。 响应于配置数据，例如，转向逻辑可以将每个端口耦合到一个或所有本地存储器组，或者耦合到一个或所有非本地存储体。

    CHANNEL DEPTH ADJUSTMENT IN MEMORY SYSTEMS
    83.
    发明申请
    CHANNEL DEPTH ADJUSTMENT IN MEMORY SYSTEMS 审中-公开
    存储系统中的通道深度调整

    公开(公告)号：US20120272031A1

    公开(公告)日：2012-10-25

    申请号：US13089621

    申请日：2011-04-19

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G06F12/02

    CPC classification number: G06F13/1678 ,  G06F12/0607 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

    Abstract translation: 描述存储器件，系统和方法，例如包括可动态配置的通道深度的存储器件。 描述了基于硬件和/或软件需求调整通道深度的设备，系统和方法。 一种这样的设备提供虚拟存储器操作，其中响应于不同存储器进程的要求，针对同一物理存储器区域调整通道深度。

    METHODS OF ACCESSING MEMORY CELLS, METHODS OF DISTRIBUTING MEMORY REQUESTS, SYSTEMS, AND MEMORY CONTROLLERS
    84.
    发明申请
    METHODS OF ACCESSING MEMORY CELLS, METHODS OF DISTRIBUTING MEMORY REQUESTS, SYSTEMS, AND MEMORY CONTROLLERS 有权
    访问记忆体的方法，分配存储器请求的方法，系统和存储器控制器

    公开(公告)号：US20120233413A1

    公开(公告)日：2012-09-13

    申请号：US13042164

    申请日：2011-03-07

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G06F12/00

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/06 ,  G06F12/0653 ,  Y02D10/13

    Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

    Abstract translation: 描述访问存储器单元的方法，分配存储器请求的方法，系统和存储器控制器。 在一种这样的方法中，其中存储器单元被划分为存储器单元的至少第一区域和存储器单元的第二区域，根据第一地址定义访问第一区域中的存储器单元，并且访问第二区域中的存储器单元 根据与第一地址定义不同的第二地址定义。 描述其他实施例。

    RANK SELECT USING A GLOBAL SELECT PIN
    85.
    发明申请
    RANK SELECT USING A GLOBAL SELECT PIN 有权
    使用全局选择PIN排列选择

    公开(公告)号：US20110216570A1

    公开(公告)日：2011-09-08

    申请号：US13109852

    申请日：2011-05-17

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G11C5/00 ,  G11C7/00

    CPC classification number: G11C8/04 ,  G11C5/066 ,  G11C8/12 ,  G11C8/16

    Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.

    Abstract translation: 公开了方法，存储器件和系统，例如通过使用减少的外部引脚来访问存储器电路的方法。 利用一个这样的系统，单个外部引脚接收全局存储器选择信号，该信号发送系统中的多个存储器电路之一的存取信号。 存储器电路可以被堆叠，并且还可以被分级存储器电路。 全局存储器选择信号可以发送到计数器。 这样的计数器可以计算全局存储器选择信号有效的时间长度，并且基于计数，向比较器发送计数信号。 比较器可以将计数信号与编程值进行比较，以确定是否访问特定的存储器芯片和/或端口。 该配置可能会在同一内存设备上的多个端口以及多个内存等级之间复制。

    ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION
    86.
    发明申请
    ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION 有权
    电子设计自动化领域区域恢复

    公开(公告)号：US20110191731A1

    公开(公告)日：2011-08-04

    申请号：US12697058

    申请日：2010-01-29

    Applicant: Robert Walker ,  Mahesh A. Iyer

    Inventor： Robert Walker ,  Mahesh A. Iyer

    IPC: G06F17/50

    CPC classification number: G06F17/50

    Abstract: Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell.

    Abstract translation: 一些实施例提供了一种便于在电子设计自动化（EDA）应用中创建设计的系统。 在操作期间，系统确定用于处理设计中的一组单元的处理顺序。 在一些实施例中，处理顺序可以是反向级别化的处理顺序。 接下来，系统可以根据处理顺序选择用于执行区域恢复的单元。 然后，系统可以暂时对所选择的小区执行区域恢复操作。 接下来，系统可以确定所选择的单元周围的区域。 接下来，系统可以在区域内传播到达时间，以在该区域的端点处获得更新的松弛值。 系统可以计算端点处的一个或多个时序度量。 如果更新的松弛值不降低端点处的定时度量，则系统可以接受所选小区的区域恢复操作。

    CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE
    87.
    发明申请
    CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE 有权
    内存处理器中的条件操作

    公开(公告)号：US20100313000A1

    公开(公告)日：2010-12-09

    申请号：US12478527

    申请日：2009-06-04

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G06F9/305 ,  G06F9/302

    CPC classification number: G06F9/3001 ,  G06F9/30072 ,  G06F9/3877 ,  G06F9/3885 ,  G06F15/7821 ,  Y02D10/12 ,  Y02D10/13

    Abstract: The present techniques provide an internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.

    Abstract translation: 本技术提供了被配置为例如并行地选择性地执行指令的存储器件的内部处理器。 一个这样的内部处理器包括多个算术逻辑单元（ALU），每个算术逻辑单元连接到条件掩蔽逻辑，并且每个被配置为处理条件指令。 条件指令可以由存储器件的定序器接收。 一旦接收到条件指令，定序器就可以启用ALU的条件屏蔽逻辑。 定序器可以将信号切换到条件屏蔽逻辑，使得如果已经满足条件指令的条件，则屏蔽逻辑屏蔽某些指令，并且如果条件未被满足则屏蔽其他指令。 在一个实施例中，内部处理器中的每个ALU可以并行地选择性地执行指令。

    INTERNAL PROCESSOR BUFFER
    88.
    发明申请
    INTERNAL PROCESSOR BUFFER 有权
    内部处理器缓冲器

    公开(公告)号：US20100312999A1

    公开(公告)日：2010-12-09

    申请号：US12478457

    申请日：2009-06-04

    Applicant: Robert Walker

    Inventor： Robert Walker

    IPC: G06F12/08 ,  G06F9/302 ,  G06F9/305

    CPC classification number: G11C19/00 ,  G06F9/3877 ,  G06F15/7821 ,  G06F15/785 ,  Y02D10/12 ,  Y02D10/13

    Abstract: One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a compute engine which performs operations on operands retrieved from the buffer, and stores results of the operations to the buffer. Such a compute engine buffer includes a compute buffer having storage units which may be electrically connected or isolated, based on the size of the operands to be stored and the configuration of the compute engine. The compute engine buffer further includes a data buffer, which may be a simple buffer. Operands may be copied to the data buffer before being copied to the compute buffer, which may save additional clock cycles for the compute engine, further increasing the compute engine efficiency.

    Abstract translation: 一种或多种本技术提供了一种配置成操纵数据并提高计算引擎效率的计算引擎缓冲器。 一个这样的计算引擎缓冲器连接到计算引擎，该计算引擎对从缓冲器检索的操作数执行操作，并将操作的结果存储到缓冲器。 这样的计算引擎缓冲器包括基于要存储的操作数的大小和计算引擎的配置的具有可以电连接或隔离的存储单元的计算缓冲器。 计算引擎缓冲器还包括数据缓冲器，其可以是简单缓冲器。 在复制到计算缓冲区之前，操作数可以复制到数据缓冲区，这可能为计算引擎节省额外的时钟周期，进一步提高了计算引擎的效率。

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