公开(公告)号：US07247905B2

公开(公告)日：2007-07-24

申请号：US10813352

申请日：2004-03-30

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US20070047293A1

公开(公告)日：2007-03-01

申请号：US11161962

申请日：2005-08-24

申请人： Jack Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Geng Wang

发明人： Jack Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Geng Wang

IPC分类号： G11C11/24

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：US20120205732A1

公开(公告)日：2012-08-16

申请号：US13454635

申请日：2012-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

摘要翻译： 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

公开(公告)号：US07923815B2

公开(公告)日：2011-04-12

申请号：US11969986

申请日：2008-01-07

申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

IPC分类号： H01L21/02

CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。

公开(公告)号：US07723201B2

公开(公告)日：2010-05-25

申请号：US11306718

申请日：2006-01-09

申请人： Kangguo Cheng ,  Geng Wang

发明人： Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L29/66181 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/1087

摘要： A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the and directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.

摘要翻译： 一种制造器件的方法包括将不同形态的沟槽形成衬底。 在上表面，沟槽具有相对于彼此的不同取向。 在一个方面，用于沟槽的窗口沿着硅衬底的<100>和<110>方向排列。 不同形态的沟槽可以形成为具有不同电容电平的电容器。 还包括通过该方法制备的装置。

公开(公告)号：US20100032742A1

公开(公告)日：2010-02-11

申请号：US12186780

申请日：2008-08-06

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

公开(公告)号：US07485525B2

公开(公告)日：2009-02-03

申请号：US11306749

申请日：2006-01-10

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

摘要翻译： 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。 这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。 第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。 在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

公开(公告)号：US07445987B2

公开(公告)日：2008-11-04

申请号：US11756927

申请日：2007-06-01

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US07326986B2

公开(公告)日：2008-02-05

申请号：US11306669

申请日：2006-01-06

申请人： Kangguo Cheng ,  Geng Wang

发明人： Kangguo Cheng ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/945 ,  H01L27/10867

摘要： A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.

公开(公告)号：US07319259B2

公开(公告)日：2008-01-15

申请号：US10904528

申请日：2004-11-15

申请人： Kangguo Cheng ,  Geng Wang

发明人： Kangguo Cheng ,  Geng Wang

IPC分类号： H01L29/76

CPC分类号： H01L22/34 ,  H01L27/1087 ,  H01L29/8605 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.