公开(公告)号：US06809968B2

公开(公告)日：2004-10-26

申请号：US10368068

申请日：2003-02-18

申请人： Kenneth W. Marr ,  John D. Porter

发明人： Kenneth W. Marr ,  John D. Porter

IPC分类号： G11C700

CPC分类号： G11C11/412 ,  G11C5/147 ,  G11C11/417

摘要： Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

摘要翻译： 为温度补偿阈值电压VT提供系统和方法。 通过提供温度补偿VTN，LL4TCMOS SRAM单元的温度变化相关的稳定性问题减少了。 根据一个实施例，VBB电位的基于温度的调制利用温度补偿电压对三阱晶体管进行背偏置，以向下拉晶体管提供相对于平坦或相对平坦的温度补偿VTN 温度。 一个实施例提供了一种偏置发生器，包括耦合到晶体管的主体端子的电荷泵和耦合到电荷泵的比较器。 比较器包括接收参考电压的第一输入端，接收VT相关电压的第二输入端和向电荷泵呈现控制信号的输出，并使电荷泵有选择地将晶体管的体电极充电至 补偿温度变化。

公开(公告)号：US06741027B1

公开(公告)日：2004-05-25

申请号：US09895699

申请日：2001-06-29

申请人： William J. Cummings ,  Kris E. Sahlstrom ,  Shiyou Pei ,  Bob L. Mackey ,  Arthur J. Learn ,  John D. Porter ,  Theodore S. Fahlen

发明人： William J. Cummings ,  Kris E. Sahlstrom ,  Shiyou Pei ,  Bob L. Mackey ,  Arthur J. Learn ,  John D. Porter ,  Theodore S. Fahlen

IPC分类号： H01J162

CPC分类号： H01J29/94 ,  H01J1/304 ,  H01J29/06 ,  H01J29/085 ,  H01J2201/02 ,  H01J2329/00 ,  H01J2329/863 ,  H01J2329/8645 ,  H01J2329/8665

摘要： A protected faceplate structure of a field emission display device is disclosed in one embodiment. Specifically, in one embodiment, the present invention recites a faceplate of a field emission display device wherein the faceplate of the field emission display device is adapted to have phosphor containing areas disposed above one side thereof. The present embodiment is further comprised of a barrier layer which is disposed over the one side of said faceplate which is adapted to have phosphor containing areas disposed thereabove. The barrier layer of the present embodiment is adapted to prevent degradation of the faceplate. Specifically, the barrier layer of the present embodiment is adapted to prevent degradation of the faceplate due to electron bombardment by electrons directed towards the phosphor containing areas.

摘要翻译： 在一个实施例中公开了场致发射显示装置的受保护的面板结构。 具体地说，在一个实施例中，本发明叙述场致发射显示装置的面板，其中场致发射显示装置的面板适于具有设置在其一侧上方的荧光体容纳区域。 本实施例还包括阻挡层，该阻挡层设置在所述面板的一侧上，其适于具有设置在其上的荧光体容纳区域。 本实施例的阻挡层适于防止面板的劣化。 具体而言，本实施方式的阻挡层适于防止由于朝向含荧光体区域的电子的电子轰击引起的面板的劣化。

公开(公告)号：US06724218B2

公开(公告)日：2004-04-20

申请号：US10336355

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K190175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06545560B1

公开(公告)日：2003-04-08

申请号：US09924658

申请日：2001-08-08

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

公开(公告)号：US06516363B1

公开(公告)日：2003-02-04

申请号：US09369515

申请日：1999-08-06

申请人： John D. Porter ,  William N. Thompson ,  Larren Gene Weber

发明人： John D. Porter ,  William N. Thompson ,  Larren Gene Weber

IPC分类号： G06F1314

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066

摘要： Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

摘要翻译： 系统，数据路径和传输数据的方法。 通过利用系统，数据路径和方法，可以以单速率或双速率传输数据。 本发明的一个实施例提供一种具有数据单元，输出寄存器和保持寄存器的系统。 输出寄存器耦合到数据单元。 保持寄存器耦合到数据单元和输出寄存器。 来自数据单元的数据基本上同时传送到输出寄存器和保持寄存器，然后将来自保持寄存器的数据传递给输出寄存器。 数据可以从输出寄存器输出。

公开(公告)号：US06331766B1

公开(公告)日：2001-12-18

申请号：US09692472

申请日：2000-10-20

申请人： Kent M. Kalpakjian ,  John D. Porter

发明人： Kent M. Kalpakjian ,  John D. Porter

IPC分类号： G05F144

CPC分类号： G05F1/466

摘要： A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

摘要翻译： 公开了一种频率感测NMOS电压调节器。 NMOS源极跟随器晶体管具有连接到预定栅极电压的栅极，通过PMOS开关晶体管耦合到外部电源电压的漏极和连接到负载的源极。 PMOS晶体管的栅极由延迟电路控制，通过该延迟电路从系统时钟导出的脉冲通过。 通过使用延迟电路和PMOS晶体管，将由NMOS晶体管产生的电流量作为系统时钟的周期速率的函数，并且由NMOS晶体管提供的电流跟踪频率相关的电流要求 导致在宽电流范围内电源电压Vcc的变化减小。

公开(公告)号：US06323590B1

公开(公告)日：2001-11-27

申请号：US09398369

申请日：1999-09-16

申请人： Chungdee Pong ,  John D. Porter ,  Theodore S. Fahlen ,  Christopher J. Curtin ,  Robert G. Neimeyer ,  Paul N. Ludwig

发明人： Chungdee Pong ,  John D. Porter ,  Theodore S. Fahlen ,  Christopher J. Curtin ,  Robert G. Neimeyer ,  Paul N. Ludwig

IPC分类号： H01J2902

CPC分类号： H01J61/305 ,  H01J9/185 ,  H01J9/242 ,  H01J9/261 ,  H01J29/028 ,  H01J29/864 ,  H01J31/123 ,  H01J2329/863 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8665

摘要： A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a wall which is held in place by a structure formed either on the faceplate or on the backplate. In one embodiment the supporting structure is formed by two adjacent walls that form a slot which mechanically restrains the wall. In another embodiment a slot is formed within the faceplate and the walls of the slot mechanically restrain the wall. In one embodiment wall segments are inserted into supporting structures that mechanically restrain each wall segment. In another embodiment a UV curable or a heat curable adhesive is used to maintain walls in their proper alignment and position. In yet another embodiment a conductive material is melted so as to bond conductive lines located on the wall and conductive lines located on the faceplate. This bond electrically connects the conductive lines located on the wall and the conductive lines located on the faceplate and maintains the wall in the proper alignment. The present invention eliminates the need for feet which attach to individual walls for maintaining the walls in the proper alignment.

公开(公告)号：US06288483B1

公开(公告)日：2001-09-11

申请号：US09240351

申请日：1999-01-29

申请人： Duane A. Haven ,  Arthur J. Learn ,  John D. Porter

发明人： Duane A. Haven ,  Arthur J. Learn ,  John D. Porter

IPC分类号： H01J2910

CPC分类号： H01J29/085 ,  H01J31/127

摘要： A light-emitting structure contains a plate (20), light-emissive regions (34R, 36G, and 38B) overlying the plate, and a dark region (40DR/46DC, 40IR/56DC, 60DR/66DC, or 76DR/80DR/80DC) overlying the plate and laterally surrounding each light-emissive region. In one aspect, the dark region is formed with (a) multiple first strips (40DR, 40IR, 60DR, or 76DR) extending in one direction and (b) multiple second strips (46DC, 56DC, 66DC, or 80DC) extending in another direction and also extending further away from the plate than the first strips. In another aspect, the dark region contains trapezoidally profiled strips (86), each having a width profile shaped like an upright trapezoid.

摘要翻译： 发光结构包含板（20），覆盖板上的发光区域（34R，36G和38B）和暗区域（40DR / 46DC，40IR / 56DC，60DR / 66DC或76DR / 80DR / 80DC）覆盖板并横向围绕每个发光区域。 在一个方面，黑暗区域形成有（a）在一个方向上延伸的多个第一条带（40DR，40IR，60DR或76DR）和（b）在另一个方向上延伸的多个第二条带（46DC，56DC，66DC或80DC） 方向并且还比第一条带更远离板延伸。 在另一方面，暗区域包含梯形异形带（86），每个具有形状像直立梯形的宽度轮廓。

公开(公告)号：US06180698B2

公开(公告)日：2001-01-30

申请号：US08808363

申请日：1997-02-28

申请人： John D. Porter ,  Scott J. Crane ,  Stephanie J. Oberg ,  Anthony W. Johnson

发明人： John D. Porter ,  Scott J. Crane ,  Stephanie J. Oberg ,  Anthony W. Johnson

IPC分类号： C08K534

CPC分类号： C08J3/096 ,  C08J3/09 ,  C08J5/18 ,  C08J2369/00 ,  H01J9/025 ,  H01J2329/00

摘要： A liquid chemical formulation suitable for making a thin solid polycarbonate film of highly uniform thickness is formed with polycarbonate material, a liquid that dissolves the polycarbonate, and possibly one or more other constituents. The liquid is typically capable of dissolving the polycarbonate to a concentration of at least 1% at 20° C. and 1 atmosphere. The liquid also typically has a boiling point of at least 80° C. at 1 atmosphere. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derivative, and cyclohexanone. In forming the polycarbonate-containing film, a liquid film (36A) of the liquid chemical formulation is formed over a substructure (30). The liquid film is processed to largely remove the liquid and convert the polycarbonate into a solid film (38).

摘要翻译： 用聚碳酸酯材料，可溶解聚碳酸酯的液体以及可能的一种或多种其它组分形成适于制备厚度均匀的薄的固体聚碳酸酯薄膜的液体化学制剂。 该液体通常能够在20℃和1个大气压下将聚碳酸酯溶解至少1％的浓度。 该液体通常在1个大气压下的沸点至少为80℃。 液体的实例包括吡啶，环取代的吡啶衍生物，吡咯，环取代的吡咯衍生物，吡咯烷，吡咯烷衍生物和环己酮。 在形成含聚碳酸酯的膜中，在子结构（30）上形成液体化学制剂的液膜（36A）。 处理液膜以大量去除液体并将聚碳酸酯转化成固体膜（38）。

公开(公告)号：US6040713A

公开(公告)日：2000-03-21

申请号：US64531

申请日：1998-04-22

申请人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

发明人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

IPC分类号： H03K5/02 ,  H03K5/12 ,  H03K5/1252 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K5/023 ,  H03K5/12 ,  H03K5/1252

摘要： A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

摘要翻译： 具有第一和第二输入端子和输出端子的缓冲器。 缓冲器还包括具有输入端和输出端的快速边沿驱动器，输入端连接到缓冲器的第一输入端，输出端连接到缓冲器的输出端。 提供具有输入端子和输出端子的屏蔽电路，输入端子连接到缓冲器的第二输入端子。 该缓冲器还包括具有输入端和输出端的恢复电路，输入端连接到屏蔽电路的输出端，输出端连接到缓冲器的输出端。