公开(公告)号：US06847198B2

公开(公告)日：2005-01-25

申请号：US10443043

申请日：2003-05-22

申请人： Kent M. Kalpakjian ,  John D. Porter

发明人： Kent M. Kalpakjian ,  John D. Porter

IPC分类号： G05F1/46 ,  G05F1/44 ,  G05F1/40

CPC分类号： G05F1/466

摘要： A frequency sensing voltage regulator is disclosed. A source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a switching transistor, and a source connected to a load. The gate of the switching transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the switching transistor, the amount of current produced by the source follower transistor is made a function of the cycle rate of the system clock and the current provided by the source follower transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

摘要翻译： 公开了一种频率感测电压调节器。 源极跟随器晶体管具有连接到预定栅极电压的栅极，通过开关晶体管耦合到外部电源电压的漏极和连接到负载的源极。 开关晶体管的栅极由延迟电路控制，通过该延迟电路从系统时钟导出的脉冲通过。 通过使用延迟电路和开关晶体管，由源极跟随器晶体管产生的电流量作为系统时钟的周期速率的函数，并且由源极跟随器晶体管提供的电流跟踪频率相关的电流要求 的负载，导致在宽电流范围内电源电压Vcc的变化减小。

公开(公告)号：US06331766B1

公开(公告)日：2001-12-18

申请号：US09692472

申请日：2000-10-20

申请人： Kent M. Kalpakjian ,  John D. Porter

发明人： Kent M. Kalpakjian ,  John D. Porter

IPC分类号： G05F144

CPC分类号： G05F1/466

摘要： A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

摘要翻译： 公开了一种频率感测NMOS电压调节器。 NMOS源极跟随器晶体管具有连接到预定栅极电压的栅极，通过PMOS开关晶体管耦合到外部电源电压的漏极和连接到负载的源极。 PMOS晶体管的栅极由延迟电路控制，通过该延迟电路从系统时钟导出的脉冲通过。 通过使用延迟电路和PMOS晶体管，将由NMOS晶体管产生的电流量作为系统时钟的周期速率的函数，并且由NMOS晶体管提供的电流跟踪频率相关的电流要求 导致在宽电流范围内电源电压Vcc的变化减小。

公开(公告)号：US06586916B2

公开(公告)日：2003-07-01

申请号：US09947522

申请日：2001-09-07

申请人： Kent M. Kalpakjian ,  John D. Porter

发明人： Kent M. Kalpakjian ,  John D. Porter

IPC分类号： G05F144

CPC分类号： G05F1/466

摘要： A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

公开(公告)号：US06175221B1

公开(公告)日：2001-01-16

申请号：US09386312

申请日：1999-08-31

申请人： Kent M. Kalpakjian ,  John D. Porter

发明人： Kent M. Kalpakjian ,  John D. Porter

IPC分类号： G05F144

CPC分类号： G05F1/466

摘要： A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

公开(公告)号：US08587984B2

公开(公告)日：2013-11-19

申请号：US12847625

申请日：2010-07-30

申请人： Pradeep Ramani ,  John D. Porter

发明人： Pradeep Ramani ,  John D. Porter

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32

摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

摘要翻译： 本公开包括用于操作电阻变量存储器的装置和方法。 一个设备实施例包括一组存储器单元，其中多个单元共同耦合到选择线，所述数量单元包括在多个目标阈值电阻（Rt）范围内可编程的多个数据单元，其数量对应于 数据状态，以及与数据单元交错并且在目标Rt范围的数目内可编程的多个参考单元。 上述设备实施例还包括耦合到阵列并被配置为感测与至少一个数据单元和至少一个参考单元相关联的电平的控制电路，并且将感测到的与至少一个数据单元相关联的电平与感测电平相关联 与所述至少一个参考单元确定所述至少一个数据单元的数据状态。

公开(公告)号：US08395837B2

公开(公告)日：2013-03-12

申请号：US11734458

申请日：2007-04-12

申请人： Hongqin Shi ,  Gregory Schaadt ,  James C. Dunphy ,  Dmitri Simonian ,  John D. Porter

发明人： Hongqin Shi ,  Gregory Schaadt ,  James C. Dunphy ,  Dmitri Simonian ,  John D. Porter

IPC分类号： G02B26/00

CPC分类号： B81B3/0005 ,  B81B2201/042 ,  B81C2201/112 ,  G02B26/0833 ,  H01L21/02046 ,  H01L21/02164 ,  H01L21/3121

摘要： A releasing and post-releasing method for making a micromirror device and a micromirror array device are disclosed herein. The releasing method removes the sacrificial materials in the micromirror and micromirror array so as to enabling movements of the movable elements in the micromirror and micromirror array device. The post-releasing method is applied to improve the performance and quality of the released micromirrors and micromirror array devices.

摘要翻译： 本文公开了用于制造微镜器件和微镜阵列器件的释放和释放方法。 释放方法去除了微反射镜和微镜阵列中的牺牲材料，以便使得微镜和微镜阵列器件中的可移动元件能够移动。 应用后释放方法来提高释放的微镜和微镜阵列器件的性能和质量。

公开(公告)号：US20110242878A1

公开(公告)日：2011-10-06

申请号：US13159288

申请日：2011-06-13

申请人： Jennifer Taylor ,  John D. Porter

发明人： Jennifer Taylor ,  John D. Porter

IPC分类号： G11C11/00 ,  G11C7/12

CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C27/005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2213/72 ,  G11C2213/79

摘要： Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

摘要翻译： 公开了用于测量多个存储元件的电阻的方法。 存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。 此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。

公开(公告)号：US08009487B2

公开(公告)日：2011-08-30

申请号：US12721290

申请日：2010-03-10

申请人： John D. Porter

发明人： John D. Porter

IPC分类号： G11C7/10 ,  G11C5/02

CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。

公开(公告)号：US20100296331A1

公开(公告)日：2010-11-25

申请号：US12847625

申请日：2010-07-30

申请人： Pradeep Ramani ,  John D. Porter

发明人： Pradeep Ramani ,  John D. Porter

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32

摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

摘要翻译： 本公开包括用于操作电阻变量存储器的装置和方法。 一个设备实施例包括一组存储器单元，其中多个单元共同耦合到选择线，所述数量单元包括在多个目标阈值电阻（Rt）范围内可编程的多个数据单元，其数量对应于 数据状态，以及与数据单元交错并且在目标Rt范围的数目内可编程的多个参考单元。 上述设备实施例还包括耦合到阵列并被配置为感测与至少一个数据单元和至少一个参考单元相关联的电平的控制电路，并且将感测到的与至少一个数据单元相关联的电平与感测电平相关联 与所述至少一个参考单元确定所述至少一个数据单元的数据状态。

公开(公告)号：US20100177574A1

公开(公告)日：2010-07-15

申请号：US12721290

申请日：2010-03-10

申请人： John D. Porter

发明人： John D. Porter

IPC分类号： G11C7/10 ,  H01R43/00 ,  G11C11/00

CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。