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公开(公告)号：US20200321055A1
公开(公告)日：2020-10-08
申请号：US16907639
申请日：2020-06-22
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
Abstract: Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.
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82.发明申请公开(公告)号：US20200243147A1
公开(公告)日：2020-07-30
申请号：US16257074
申请日：2019-01-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
Abstract: Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.
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83.发明授权公开(公告)号：US10726929B1
公开(公告)日：2020-07-28
申请号：US16257074
申请日：2019-01-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
Abstract: Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.
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公开(公告)号：US10726920B2
公开(公告)日：2020-07-28
申请号：US16200007
申请日：2018-11-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
Abstract: Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.
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85.发明授权公开(公告)号：US10559370B2
公开(公告)日：2020-02-11
申请号：US15928976
申请日：2018-03-22
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Piyush Dak , Wei Zhao , Huai-Yuan Tseng , Deepanshu Dutta , Mohan Dunga
Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.
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Patent Agency Ranking
公开(公告)号：US10559365B2
公开(公告)日：2020-02-11
申请号：US15937420
申请日：2018-03-27
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-yuan Tseng , Deepanshu Dutta
IPC: G11C16/30 , G11C16/08 , G11C16/24 , G11C16/04 , H01L23/528 , H01L27/1157 , H01L27/11524 , H01L29/08 , H01L29/10
Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
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公开(公告)号：US10541038B2
公开(公告)日：2020-01-21
申请号：US16205165
申请日：2018-11-29
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Xiang Yang , Zhenming Zhou , Deepanshu Dutta , Huai-Yuan Tseng
Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
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公开(公告)号：US20190392909A1
公开(公告)日：2019-12-26
申请号：US16014850
申请日：2018-06-21
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
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公开(公告)号：US20190392893A1
公开(公告)日：2019-12-26
申请号：US16019456
申请日：2018-06-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Dengtao Zhao , Huai-Yuan Tseng , Deepanshu Dutta , Zhongguang Xu , Yanli Zhang , Jin Liu
Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.
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公开(公告)号：US10482984B2
公开(公告)日：2019-11-19
申请号：US15952752
申请日：2018-04-13
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G11C16/34 , H01L27/11556 , H01L27/11582 , G11C16/04 , G11C16/10 , G11C16/26
Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.
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