公开(公告)号：US20120327557A1

公开(公告)日：2012-12-27

申请号：US13531242

申请日：2012-06-22

申请人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

发明人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

IPC分类号： H01G4/12

CPC分类号： H01G4/1272 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30

摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.

摘要翻译： 提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度 在200μm以下的条件下。

公开(公告)号：US06919748B2

公开(公告)日：2005-07-19

申请号：US10377722

申请日：2003-03-04

申请人： Byoung Hwa Lee ,  Nam Chul Kim ,  Jeong Ho Yoon ,  Sang Soo Park

发明人： Byoung Hwa Lee ,  Nam Chul Kim ,  Jeong Ho Yoon ,  Sang Soo Park

IPC分类号： H01P1/20 ,  H01P1/203 ,  H01P1/205 ,  H03H7/01

CPC分类号： H01P1/20345

摘要： An dielectric laminated filter improves a skirt characteristic to shift am attenuation pole to a transmitting frequency band while maintaining the same band width of the transmitting frequency band and includes a dielectric block laminated with a plurality of dielectric sheets, ground electrodes formed on front and rear sides of the dielectric block, input and output electrodes formed on both sides of the dielectric body to be separated from the ground electrodes, an inductor pattern having two portions disposed parallel to the resonator patterns coupled to the input and output electrodes and a connecting portion coupling the two portions to induce an inductance coupling with the resonator patterns coupled to the input and output electrodes to improve a filter response characteristic by adjusting the inductance coupling.

摘要翻译： 电介质层压滤波器改善裙边特性，以将衰减极点移动到发射频带，同时保持发射频带的相同带宽，并且包括层叠有多个电介质片的介质块，形成在前侧和后侧的接地电极 介电块的形成在电介体的两侧的输入和输出电极与接地电极分离;电感器图案，具有平行于耦合到输入和输出电极的谐振器图案设置的两个部分，以及连接部分 两部分，以引起与耦合到输入和输出电极的谐振器图案的电感耦合，以通过调节电感耦合来改善滤波器响应特性。

公开(公告)号：US20130050899A1

公开(公告)日：2013-02-28

申请号：US13451251

申请日：2012-04-19

申请人： Hyung Joon Kim ,  Byoung Hwa Lee

发明人： Hyung Joon Kim ,  Byoung Hwa Lee

IPC分类号： H01G4/12

CPC分类号： H01G4/30 ,  H01G4/005 ,  H01G4/224 ,  H01G4/232

摘要： There is provided a multilayer ceramic capacitor including: a ceramic body; first and second internal electrodes including respective lead-out portions having an overlapping area, the overlapping area being exposed to one surface of the ceramic body; first and second external electrodes formed on the one surface of the ceramic body and connected to the respective lead-out portions; and an insulation layer formed on the one surface of the ceramic body to which the lead-out portions are exposed.

摘要翻译： 提供了一种多层陶瓷电容器，包括：陶瓷体; 第一和第二内部电极包括具有重叠区域的相应引出部分，所述重叠区域暴露于所述陶瓷体的一个表面; 第一和第二外部电极，其形成在陶瓷体的一个表面上并连接到相应的引出部分; 以及形成在所述引出部露出的所述陶瓷体的一个表面上的绝缘层。

公开(公告)号：US20060018081A1

公开(公告)日：2006-01-26

申请号：US11068757

申请日：2005-03-02

申请人： Byoung Hwa Lee ,  Dong Park ,  Min Park ,  Sang Park ,  Chang Shim ,  Kyung Hwang

发明人： Byoung Hwa Lee ,  Dong Park ,  Min Park ,  Sang Park ,  Chang Shim ,  Kyung Hwang

IPC分类号： H01G4/06

CPC分类号： H01G4/012 ,  H01G4/30

摘要： A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.

公开(公告)号：US20060092595A1

公开(公告)日：2006-05-04

申请号：US11264486

申请日：2005-11-01

申请人： Byoung Hwa Lee ,  Hiroki Sato ,  Chang Shim ,  Sang Park ,  Hae Chung ,  Dong Park ,  Min Park ,  Hyun Yi ,  Min Kwon ,  Seung Han

发明人： Byoung Hwa Lee ,  Hiroki Sato ,  Chang Shim ,  Sang Park ,  Hae Chung ,  Dong Park ,  Min Park ,  Hyun Yi ,  Min Kwon ,  Seung Han

IPC分类号： H01G4/228

CPC分类号： H05K1/0231 ,  H01G2/065 ,  H01G4/228 ,  H01G4/30 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.